bt829bkrf ETC-unknow, bt829bkrf Datasheet - Page 20

• Manufacturer Part Number: bt829bkrf
• Description: Video Streamii Decoders
• Manufacturer: ETC-unknow

10
1.0 Functional Description
1.2 Pin Descriptions
Table 1-2. Pin Descriptions Grouped By Pin Function (3 of 4)
91
86
85
12
13
16
17
97
99
80
34
36
37
32
Pin #
I/O
O
O
O
O
A
A
A
A
I
I
I
I
I
I
Pin Name
NUMXTAL
VACTIVE
PWRDN
OEPOLE
CLKx1
CLKx2
XT0O
XT1O
XT0I
XT1I
TMS
TDO
TCK
TDI
A logical high on this pin puts the device into power-down mode. This is equivalent
to programming CLK_SLEEP high in the ADC register.
Vertical Blanking Output (TTL compatible). The falling edge of VACTIVE indicates the
beginning of the active video lines in a field. This occurs VDELAY/2 lines after the ris-
ing edge of VRESET . The rising edge of VACTIVE indicates the end of active video
lines and occurs ACTIVE_LINES/2 lines after the falling edge of VACTIVE. VACTIVE is
output following the rising edge of CLKx1.
Note: The polarity of the pin is programmable through the VPOLE register.
A logical low on this pin allows the Bt829B/827B to power up in the same manner as
the Bt829/827. A logical high on this pin, followed by a device reset will TRISTATE
the video outputs, sync outputs, and clock outputs.
Clock Zero pins. A 28.64 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT0I.
CMOS level inputs must be used. This clock source is selected for NTSC input
sources. When the chip is configured to decode PAL but not NTSC (and therefore
only one clock source is needed), the 35.47 MHz source is connected to this port
(XT0).
Clock One pins. A 35.47 MHz (8*Fsc) fundamental (or third harmonic) crystal can be
tied directly to these pins, or a single-ended oscillator can be connected to XT1I.
CMOS level inputs must be used. This clock source is selected for PAL input sources.
If only NTSC or PAL is being decoded, and therefore only XT0I and XT0O are con-
nected to a crystal, XT1I should be tied either high or low, and XT1O must be left
floating.
1x clock output (TTL compatible). The frequency of this clock is 4*Fsc (14.31818
MHz for NTSC or 17.73447 MHz for PAL).
2x clock output (TTL compatible). The frequency of this clock is 8*Fsc (28.63636
MHz for NTSC, or 35.46895 MHz for PAL).
Crystal Format Pin. This pin is set to indicate whether one or two crystals are present
so that the Bt829B can select XT1 or XT0 as the default in auto format mode. A logi-
cal 0 on this pin indicates one crystal is present. A logical 1 indicates two crystals are
present. This pin is internally pulled down to ground with an effective 18 K resis-
tance.
Test Clock (TTL compatible). Used to synchronize all JTAG test structures. When
JTAG operations are not being performed, this pin must be driven to a logical low.
Test Mode Select (TTL compatible). JTAG input pin whose transitions drive the JTAG
state machine through its sequences. When JTAG operations are not being per-
formed, this pin must be left floating or tied high.
Test Data Input (TTL compatible). JTAG pin used for loading instruction into the TAP
controller or for loading test vector data for boundary-scan operation. When JTAG
operations are not being performed, this pin must be left floating or tied high.
Test Data Output (TTL compatible). JTAG pin used for verifying test results of all
JTAG sampling operations. This output pin is active for certain JTAG operations and
will be three-stated at all other times.
Clock Interface Pins
D829BDSA
JTAG Pins
Description
VideoStream II Decoders
Bt829B/827B