mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 206

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

Port Integration Module (PIM)
4.2.1
206
TXD_BG[1:2]/IF_SEL[1:0] PHY Data transmitter output / Host interface select
A[6:1]/XADDR[14:19]
BSEL[1:0]#/DBG[0:1]
A[12:11]/ACS[2:1]
D[15:8]/PB[0:7]
A10/ECLK_CC
WE#/RW_CC#
D[7:0]/PA[0:7]
RXD_BG[2:1]
CHICLK_CC
CE#/LSTRB
TXEN[2:1]#
OE#/ACS0
INT_CC#
CLKOUT
RESET#
Name
A[7:9]
TEST
Functional Mode
AMI address bus / HCS12 expanded address lines.
A1-LSB of the AMI address bus,
XADDR14-LSB of the HCS12 expanded address lines
AMI address bus
AMI read output enable signal / HCS12 address select input
AMI address bus / HCS12 address select inputs
AMI byte select / Debug strobe point
AMI data bus / HCS12 multiplexed address/data bus.
D15 is the MSB of the AMI data bus,
PB0 is the LSB of the HCS12 address/data bus
AMI data bus / HCS12 multiplexed address/data bus.
D0 is the LSB of the AMI data bus,
PA7 is the MSB of the HCS12 address/data bus
AMI chip select signal / HCS12 low-byte strobe signal
AMI write enable signal/ HCS12 read/write select signal
AMI address bus/ HCS12 clock inputHCS12 interface, clock
input
PHY Data receiver input
Transmit enable for PHY
External CHI clock input selectable
Controller clock output selectable between disabled,
4/10/40 MHz
Hardware reset input
Controller interrupt output
Factory Test mode select — must be tied to logic low in
application
Table 4-1. Pin Functions (Functional Mode)
MFR4300 Data Sheet, Rev. 3
Physical Layer Interface
Clock Interface
Function
Host Interface
Other
Input/Output
Input/Output
Input/Output
Input/Output
Direction
Output
Output
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Freescale Semiconductor
Configuration
DC/PU/PD
DC/PU/PD
DC/PU/PD
Special
DC/OD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
PU/PD
DC
DC
DC
PD
-
-
1