mfr4300 Freescale Semiconductor, Inc, mfr4300 Datasheet - Page 180

• Manufacturer Part Number: mfr4300
• Description: Flexray Communication Controllers
• Manufacturer: Freescale Semiconductor, Inc

FlexRay Module (FLEXRAYV2)
3.4.9.2
The receive FIFO control and configuration data are given in
Configuration Data”.
The first step is the allocation of the required amount of FRM for the FlexRay window. This includes the
allocation of the message buffer header area and the allocation of the message buffer data fields. For more
details see
The second step is the programming of the configuration data register while the PE is in
The following steps configure the layout of the FIFO.
The FIFO filters are configured through the fifo filter registers.
3.4.9.3
The frame reception to the receive FIFO is enabled, if for a certain slots no message buffer is assigned or
subscribed. In this case the FIFO filter path shown in
When the receive FIFO filter path indicates that the received frame must be appended to the FIFO, the
FlexRay module writes the received frame header and slot status into the message buffer header field
indicated by the internal FIFO header write index. The payload data are written in the message buffer data
field. If the status of the received frame indicates a valid frame, the internal FIFO header write index is
updated and the fifo not-empty interrupt flag FNEAIF/FNEBIF in the
Register (GIFER)
3.4.9.4
If the fifo not-empty interrupt flag FNEAIF/FNEBIF in the
(GIFER)
application.
The receive FIFO does not require locking to access the message buffers. To access the message the
application first reads the receive FIFO read index RDIDX from the
(RFARIR)
message buffer header field of the next message buffer that contains valid data. The application can access
the message data as described in
message buffer data and status information, it writes ‘1’ to the fifo not-empty interrupt flags FNEAIF or
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The number of the first message buffer header index that belongs to the FIFO is written into the
Receive FIFO Start Index Register
The depth of the FIFO is written into the FIFO_DEPTH field in the
Register
The length of the message buffer data field for the FIFO is written into the ENTRY_SIZE field in
the
is set, the receive FIFO contains valid received messages, which can be accessed by the
Section 3.4.4, “FlexRay Memory Layout”.
Receive FIFO Depth and Size Register
or
Receive FIFO Configuration
Receive FIFO Reception
Receive FIFO Message Access
Receive FIFO B Read Index Register
To ensure, that the read index RDIDX always points to a message buffer that
contains valid data, the receive FIFO must have at least 2 entries.
(RFDSR).
is set.
The configuration of the receive FIFOs consists of two steps.
Section 3.4.3.3, “Receive FIFO”.
MFR4300 Data Sheet, Rev. 3
(RFSIR).
NOTE
(RFDSR).
(RFBRIR), respectively. This index points to the
Figure 3-129
Global Interrupt Flag and Enable Register
Section 3.4.3.7, “Receive FIFO Control and
When the application has read all
is activated.
Receive FIFO A Read Index Register
Global Interrupt Flag and Enable
Receive FIFO Depth and Size
Freescale Semiconductor
POC:config.