lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 6

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

LRS1338A
FLASH MEMORY*
New Features
compatibility with SHARP’s LH28F800BG-L.
• SmartVoltage technology
• Enhanced suspend capabilities
• Boot block architecture
• V
• Allow V
Product Overview
Voltage flash memory organized as 512K-word of 16
bits. The 512K-word of data is arranged in two 4K-word
boot blocks, six 4K-word parameter blocks and fifteen
32K-word main blocks which are individually erasable
in-system. The memory map is shown in Figure 4.
and V
system performance and power expectations. In addi-
tion to flexible erase and program voltages, the dedi-
cated V
V
cally configures the device for optimized read and write
operations.
6
PP
block erase and word write operations. Designs that
switch V
sure that the V
The LRS1388A flash memory maintains backwards
Please note the following important differences:
The LRS1338A is a high-performance 8M Smart-
SmartVoltage technology provides a choice of V
Internal V
Table 3. V
PPLK
PP
V
2.7 V to 3.6 V
V
PPLK
PP
CC
combinations, as shown in Table 3, to meet
has been lowered to 1.5 V to support 3.0 V
PP
PP
pin gives complete data protection when
Voltage
.
CC
connection to 3.0 V.
off during read operations should make
CC
and V
PP
and V
voltage transitions to GND.
PP
PP
detection circuitry automati-
Voltage Combinations
2.7 V to 3.6 V
V
PP
Voltage
CC
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An inter-
nal Write State Machine (WSM) automatically executes
the algorithms and timings necessary for block erase
and word write operations.
32K-word blocks typically within 1.14 seconds, 4K-
word blocks typically within 0.38 seconds independent
of other blocks. Each block can be independently
erased 100,000 times. Block erase suspend mode
allows system software to suspend block erase to read
or write data from any other block.
of the device’s 32K-word blocks typically within 44.6 µs,
4K-word blocks typically within 45.9 µs. Word write sus-
pend mode enables the system to read data or execute
code from any other flash memory array location.
erase or word write for boot block must not be carried
out by WP to LOW and RP to V
erase or word write operation is finished.
cial temperature range (-40°C to +85°C) and V
ply voltage range of 2.7 V to 3.6 V.
stantially reduces active current when the device is in
static mode (addresses not switching). In APS mode,
the typical I
standby mode is enabled. When the RP pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing reset. A reset time (t
switching HIGH until outputs are valid. Likewise, the
device has a wake time (t
writes to the CUI are recognized. With RP at GND, the
WSM is reset and the status register is cleared.
NOTE: *In the Flash Memory section all reference to pins, com-
mands, voltage, etc. refer only to the Flash portion of this chip.
A Command User Interface (CUI) serves as the
A block erase operation erases on e of the device’s
Writing memory data is performed in word increments
The boot blocks can be locked for the WP pin. Block
The status register indicates when the WSM’s block
The access time is 120 ns (t
The Automatic Power Savings (APS) feature sub-
When CE and RP pins are at V
CCR
Stacked Chip (8M Flash & 2M SRAM)
current is 1 mA at 3.3 V V
PHQV
PHEL
AVQV
IH
) is required from RP
) from RP HIGH until
.
) over the commer-
CC
, the I
CC
Data Sheet
CC
.
CC
CMOS
sup-