lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 11

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

Stacked Chip (8M Flash & 2M SRAM)
COMMAND DEFINITIONS
register, identifier codes or blocks are enabled. Placing
V
write operations.
NOTES:
1. Refer to ‘DC Characteristics’. When V
2. X can be V
3. Never hold OE LOW and WE LOW at the same time.
4. RP at GND ± 0.2 V ensures the lowest deep power-down current.
5. See ‘Read Identifier Codes Command’ for read identifier code data.
6. Command writes involving block erase or word write are reliably executed when V
7. Refer to Table 6 for valid D
NOTES:
1. Commands other than those shown in table are reserved by SHARP for
2. BUS operations are defined in Table 5.
3. X = Any valid address within the device; IA = Identifier Code Address, see Figure 5.
4. SRD = Data read from status register. See Table 9 for a description of the status register bits.
5. Following the Read Identifier Codes command, read operations access manufacturer and device codes.
6. When WP = V
7. Either 40H or 10H are recognized by the WSM as the word write setup.
Data Sheet
Read
Output Disable
Standby
Deep Power-Down
Read Identifier Codes
Write
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and Word
Write Suspend
Block Erase and Word
Write Resume
PPH
When V
See ‘DC Characteristics’ for V
Block erase or word write with V
future device implementations and should not be used.
BA = Address within the block being erased; WA = Address of memory location to be written.
WD = Data to be written at location WA. Data is latched on the rising edge of WE or CE (whichever goes HIGH first).
ID = Data read from identifier codes.
See ‘Read Identifier Codes Command’ for read identifier code data.
Attempts to issue a block erase or word write to a locked boot block while RP = V
on V
COMMAND
MODE
PP
PP
IL
enables successful block erase and word
or V
IL
V
, RP must beat V
PPLK
IH
for control pins and addresses, and V
, Read operations from the status
IN
BUS CYCLES
REQUIRED
V
V
V
V
V
during a write operations.
PPLK
IH
IH
IH
IH
IH
IH
HH
RP
V
or V
or V
or V
or V
or V
< RP < V
1
2
1
2
2
1
1
IL
and V
2
to enable block erase or word write operations.
PP
HH
HH
HH
HH
HH
PPH
V
HH
PPLK
voltages.
produce spurious results and should not be attempted.
Table 6. Command Definitions
CE
V
OPER.
V
V
V
V
, memory contents can be read, but not altered.
X
Write
Write
Write
Write
Write
Write
Write
Write
IH
IL
IL
IL
IL
Table 5. Bus Operations
2
FIRST BUS CYCLE
PPLK
OE
V
V
V
V
X
X
ADDR.
IH
IH
IL
IL
or V
WA
BA
X
X
X
X
X
X
PPH
3
mands into the CUI. Table 6 defines these commands.
WE
V
V
V
V
for V
X
X
IH
IH
IH
IL
40H or 10H
Device operations are selected by writing specific com-
DATA
PP
FFH
B0H
D0H
90H
70H
50H
20H
.
IH
See Figure 3
PP
ADDRESS
.
4
= V
1
PPH
X
X
X
X
X
OPER.
and V
Read
Read
Write
Write
SECOND BUS CYCLE
CC
2
= V
V
X
X
X
X
X
X
PP
ADDR.
CC1
WA
BA
IA
X
.
I/O
3
HIGH Z
HIGH Z
HIGH Z
D
0
D
OUT
- I/O
IN
DATA
SRD
D0H
WD
ID
15
4
LRS1338A
NOTES
1, 2, 3
3, 6, 7
NOTES
4
5
6, 7
5
6
6
6
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