lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 3

• Manufacturer Part Number: lrs1338a
• Description: Stacked Chip Flash Memory Sram
• Manufacturer: Sharp Microelectronics of the Americas

Stacked Chip (8M Flash & 2M SRAM)
GENERAL DESIGN GUIDELINES
Supply Power
the voltage is less than 0.3 V.
Power Supply and Chip Enable of Flash
Memory and SRAM
LOW simultaneously. If the two memories are active
together, they many not operate normally due to inter-
ference noises or data collision on I/O bus. Both F-V
and S-V
supply voltage at the same time except SRAM data
retention mode.
SRAM Data Retention
SRAM power switching between a system battery and
a backup battery needs careful device decoupling from
Flash Memory to prevent SRAM supply voltage from
falling lower than 2.0 V by a Flash Memory peak cur-
rent caused by transition of Flash Memory supply volt-
age or of control signals (F-CE, F-OE, and RP).
CASE 1: FLASH MEMORY IS IN STANDBY MODE
(F-V
• SRAM inputs and input/outputs except S-CE need to
• Flash Memory inputs and input/outputs except F-CE
NOTES:
1. F-CE should not be LOW when S-CE is LOW simultaneously.
2. X can be V
3. Refer to DC Characteristics. When F-V
4. Do not use in a timing that both F-OE and F-WE is LOW level.
Data Sheet
F-CE
be applied with voltages in the range of -0.3 V to
S-V
and RP need to be applied with voltages in the range
of -0.3 V to S-V
Maximum difference (between F-V
It is forbidden that both F-CE and S-CE should be
SRAM data retention is capable in three ways.
for F-V
tents can be read, but not altered.
H
H
H
H
X
L
L
L
CC
CC
= 2.7 V TO 3.6 V)
PP
CC
F-OE
+ 0.3 V or to be open (HIGH-Z).
. See DC Characteristics for V
H
H
X
X
X
X
X
L
IL
need to be applied by the recommended
or V
IH
F-WE
for control pins and addresses, and V
CC
H
H
X
X
X
X
X
L
+ 0.3 V or to be open (HIGH-Z).
F-RP
H
H
H
X
X
X
H
L
S-CE
PPLK
H
H
H
H
H
L
L
L
PP
and V
CC
V
S-OE
PPLK
H
X
X
X
X
X
X
and S-V
L
PPH
, memory con-
voltages.
PPLK
Table 2. Truth Table
S-WE
X
X
X
H
H
X
X
L
CC
or V
) of
PPH
CC
ADDRESS
X
X
X
X
X
X
X
X
CASE 2: FLASH MEMORY IS IN DEEP POWER
DOWN MODE (F-V
• SRAM inputs and input/outputs except S-CE need to
• Flash Memory inputs and input/outputs except RP
CASE 3: FLASH MEMORY POWER SUPPLY IS
TURNED OFF (F-V
• Fix RP LOW level before turning off Flash memory
• SRAM inputs and input/outputs except S-CE need to
• Flash Memory inputs and input/outputs except RP
Power Up Sequence
RP LOW. After F-V
LOW for more than 100 ns.
Device Decoupling
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE).
5. F-RP at GND ± 0.2 V ensures the lowest deep power down current.
6. Command writes involving block erase, write, or lock-bit configura-
7. Refer to Table 6 for valid D
be applied with voltages in the range of -0.3 V to
S-V
need to be applied with voltages in the range of -0.3 V
to S-V
be at the same level as F-V
power supply.
be applied with voltages in the range of -0.3 V to
S-V
need to be applied with voltages in the range of
-0.3 V to S-V
When turning on Flash memory power supply, keep
The power supply needs to be designed carefully
tion are reliably executed when F-V
block erase or word write operations with V
T
A
< -30°C produce spurious results and should not be attempted.
Flash read
Flash read
Flash write
SRAM read
SRAM read
SRAM write
Standby
Deep power down
CC
CC
1,2
CC
+ 0.3 V or to be open.
+ 0.3 V or to be open (HIGH-Z).
MODE
+ 0.3 V or to be open (HIGH-Z). RP needs to
CC
+ 0.3 V or to be open (HIGH-Z).
CC
CC
CC
= 2.7 V TO 3.6 V)
= 0 V)
reaches over 2.7 V, keep RP
IN
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
I/O
Output
Output
I/O
Input
Input
during a write operation.
0
15
CC
to
PP
or to be open.
= V
CURRENT
PPH
I
I
I
I
I
I
I
I
CC
CC
CC
CC
CC
CC
SB
SB
IH
and F-V
< F-RP < V
LRS1338A
CC
NOTE
4, 6, 7
3, 4
= V
5
5
HH
CC1
or
3