lrs1338a Sharp Microelectronics of the Americas, lrs1338a Datasheet - Page 34
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lrs1338a
Manufacturer Part Number
lrs1338a
Description
Stacked Chip Flash Memory Sram
Manufacturer
Sharp Microelectronics of the Americas
Datasheet
1.LRS1338A.pdf
(36 pages)
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LRS1338A
34
NOTES:
1. t
2. t
3. t
4. During this period, I/O pins are in the output state, therefore the input signals of
5. If CE goes LOW simultaneously with WE going LOW or after WE going LOW,
6. If CE goes HIGH simultaneously with WE going HIGH or before WE going HIGH,
in case a write ends at CE or WE going HIGH.
opposite phase to the outputs must not be applied.
the outputs remain in HIGH impedance state.
the outputs remain in HIGH impedance state.
CW
AS
WR
is measured from the address valid to the beginning of write.
is measured from the later of CE going LOW to the end of write.
is measured from the end of write to the address change. t
V
CE
ADDRESS
CC
D
WE
OUT
D
CE
IN
V
2.7 V
2.0 V
CCDR
0 V
Figure 19. Write Cycle Timing Diagram (OE LOW Fixed)
Figure 20. Data Retention Timing Diagram
t
CDR
(NOTE 2)
(NOTE 5)
t
AS
Data Retention Mode
CE
WR
V
CCDR
t
applies
AW
(NOTE 4)
t
- 0.2 V
WZ
t
WC
t
CW
(NOTE 1)
t
WP
t
DW
Stacked Chip (8M Flash & 2M SRAM)
DATA VALID
t
R
(NOTE 3)
(NOTE 3)
t
t
WR
(NOTE 6)
WR
t
DH
t
OW
Data Sheet
1338A-20
1338A-19
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