lrs1331 Sharp Microelectronics of the Americas, lrs1331 Datasheet
lrs1331
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lrs1331 Summary of contents
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... Operating current (MAX.) pin): CCW – Standby current: 15 µA (MAX.) – Data retention current: 2 µA (MAX.) pin): 15 µA DESCRIPTION CC The LRS1331 is a combination memory organized as 1,048,576 × 16-bit flash memory and 262,144 × 16-bit static RAM in one package ...
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... LRS1331 F-A F F-CE F-OE F-WE F-RP F-WP S-A S-CE S-CE S-OE S-WE S-UB 2 F-V F-V F-GND 16M (x16) BIT FLASH MEMORY (x16) BIT 2 SRAM S-LB S-V S-GND CC Figure 2. LRS1331 Block Diagram Stacked Chip (16M Flash & 4M SRAM) F-RY/ LRS1331-2 Data Sheet ...
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... Data Sheet Table 1. Pin Descriptions DESCRIPTION PPLK < PPLK LRS1331 TYPE Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input/Output Power Power Power Power Power — — ...
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... LRS1331 FLASH SRAM F-CE F-RP Read Standby L Output Disable Standby L Write Standby L Read H H Output Standby Disable H Write H Read X X Output Reset Disable X Write X Standby Standby H Reset Standby X NOTES Refer to DC Characteristics Refer to the ‘Flash Memory Command Definition’ section for valid address input and D during a write operation ...
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... Write XA 60H Write XA 60H Table 4. Identifier Codes ADDRESS ( 00000H 00001H 00003H 00003H - DQ are reserved for future use LRS1331 1 SECOND BUS CYCLE NOTES OPERATION ADDRESS DATA Read IA ID Read XA SRD Write BA D0H Write XA D0H Write ...
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... LRS1331 OPERATION F-V F-RP CCW ≤ CCWLK V IL Block Erase or Word Write > V CCWLK V IH ≤ CCWLK V IL Full Chip Erase > V CCWLK V IH ≤ CCWLK V Set Block IL Lock-Bit > V CCWLK V IH ≤ CCWLK V Clear Block IL Lock-Bit > V CCWLK ...
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... F- gruation codes after writing the Read Identifier codes command indicates permanent and block lock-bit status.. 5. SR.0 is reserved for future use and should be masked out when polling the status register. LRS1331 WBWSS DPS ...
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... BOOT BLOCK 00000 BOTTOM BOOT Figure 3. Memory Map for Flash Memory Stacked Chip (16M Flash & 4M SRAM LRS1331-3 Data Sheet ...
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... NOTE: *Sampled by not 100% tested. Data Sheet RATINGS -0 -25 to +85 OPR -65 to +125 STG -0.5 to +4.6 CCW TYP. MAX. 3.0 3 0.2 CC 0.6 . CONDITION MIN. TYP I/O UNIT NOTES °C ° UNIT NOTES MAX. UNIT LRS1331 9 ...
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... LRS1331 DC CHARACTERISTICS T = -25° 85° PARAMETER Input leakage current Output leakage current Standby Current Auto Power-Save Current Reset/Power-Down Current F-V CC Read Current Word Write or Set Lock-Bit Current Block Erase, Full Chip Erase or Clear Block Lock-BIts Current Word Write Block Erase ...
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... CONDITION 2 1.35 V 1TTL + C (50 pF) L SYMBOL t AVAV t AVQV t ELQV t PHQV t GLQV t ELQX t EHQZ t GLQX t GHQZ after the falling edge of F-OE without impact on t GLQV MIN. MAX. UNIT 600 ELQV LRS1331 11 ...
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... LRS1331 Write Cycle (F-WE Controlled -25°C to +85° PARAMETER Write Cycle Time F-RP HIGH Recovery to F-WE going to LOW F-CE Setup to F-WE going LOW F-WE Pulse Width F-WP V Setup to F-WE going HIGH IH F-V Setup to F-WE going HIGH CCW Address Setup to F-WE going HIGH Data Setup to F-WE going HIGH Data Hold from F-WE HIGH ...
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... EHGL t 0 QVVL t 0 QVSL and D for block erase or word write 2 3.6 V CCW MIN. TYP 1.1 0.15 1.2 0.6 42 27.6 0.64 6.0 16 LRS1331 MAX. UNIT NOTES ns µ 100 UNIT NOTES 1 2 MAX. 200 µs 3 200 µ ...
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... FLASH MEMORY AC CHARACTERISTICS TIMING DIAGRAMS Standby ADDRESS F-CE F-OE F-WE HIGH Z DQ F-V CC F-RP 14 Device Address Selection Address Stable t AVAV t GLQV t ELQV t GLQX t ELQX Valid Output t AVQV t PHQV Figure 4. Read Cycle Timing Diagram Stacked Chip (16M Flash & 4M SRAM) Data Valid t EHQZ t GHQZ t OH HIGH Z LRS1331-4 Data Sheet ...
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... Read status register data. 6. Write Read Array command. Figure 5. Write Cycle Timing Diagram (F-WE Controlled) Data Sheet AVWH t WHAX t t WHEH WHGL t t WHWL EHQV1 WHDX WHRL t SHWH t VPWH LRS1331 5 6 Data D Valid IN SRD t QVSL t QVVL LRS1331-5 15 ...
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... AVAV AVEH t EHAX t t WLEL EHWH EHGL t t EHEL EHQV1 ELEH t DVEH t EHDX EHRL t SHEH t VPEH Stacked Chip (16M Flash & 4M SRAM Data Valid D IN SRD t QVSL t QVVL LRS1331-6 Data Sheet ...
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... Data Sheet SYMBOL MIN. , this CC t 100 PLPH t PLRZ t 100 VPH has been CC t PLPH A. Reset During Read Array Mode t PLRZ t PLPH B. Reset During Block Erase or Word Byte Write t VPH C. F-RP Rising Timing LRS1331 MAX. UNIT NOTES ns 20 µ 1331-7 17 ...
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... LRS1331 SRAM AC ELECTRICAL CHARACTERISTICS AC Test Conditions PARAMETER Input pulse level Input rise and fall time Input and Output timing reference level Output load* NOTE: *Including scope and jig capacitance. Read Cycle T = -25°C to +85° PARAMETER Read Cycle Time ...
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... Stacked Chip (16M Flash & 4M SRAM) SRAM AC CHARACTERISTICS TIMING DIAGRAMS ADDRESS S-CE 1 S-CE 2 S-UB, S-LB S-OE D OUT NOTE: S-WE is HIGH for Read Cycle. Data Sheet ACE BLZ OLZ Figure 8. Read Cycle Timing Diagram LRS1331 BHZ t OHZ Data Valid t OH 1331-8 19 ...
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... LRS1331 ADDRESS S-CE 1 S-CE 2 S-UB, S-LB S-WE D OUT D IN NOTES write occurs during the overlap of a LOW S-CE A write begins at the latest transition among S-CE and S-WE going LOW. A write ends at the earliest transition among S-CE S-CE going LOW and S-WE going HIGH write to the end of write measured from the later of S- write ...
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... HIGH S-CE and a LOW S-WE going LOW, S-CE going HIGH 1 2 going HIGH measured from the beginning of WP going LOW or S-CE going HIGH to the end 1 2 applied in case a WR going LOW or S-WE going HIGH. 2 LRS1331 (NOTE Data Valid 1331-10 21 ...
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... LRS1331 ADDRESS S-OE S-CE 1 S-CE 2 S-UB, S-LB S-WE D OUT D IN NOTES write occurs during the overlap of a LOW S-CE A write begins at the latest transition among S-CE and S-WE going LOW. A write ends at the earliest transition among S-CE S-CE going LOW and S-WE going HIGH write to the end of write measured from the later of S- write ...
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... V 1 CCDR CDR t R ≤ 0.2 V (S-CE controlled Data Retention Mode t CDR ≥ V S- CCDR , fix the input level of S-CE between 1 2 Data Retention Mode t CDR ≤ 0.2 V S-CE 2 LRS1331 1 MIN. TYP. MAX. UNIT 1 3 µ controlled Controlled Controlled) 2 NOTES 2 ...
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... LRS1331 GENERAL DESIGN GUIDELINES Supply Power Maximum difference (between F-V the voltage is less than 0.3 V. Power Supply and Chip Enable of Flash Memory and SRAM S-CE should not be LOW and S-CE 1 HIGH when F-CE is LOW simultaneously. If the two memories are active together, they may not operate normally because of interference noises or data collision on DQ bus ...
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... SIDE VIEW 0.10 S 1.1 TYP. 0.8 TYP. H BOTTOM VIEW NOTE: Dimensions are in mm. Data Sheet INDEX +0.2 11 (See Detail) 0.4 TYP. C 1.2 TYP. 0.8 TYP φ 0. φ 0.45 ±0.05 φ 0. 0.40 TYP. DETAIL 0.35 ±0.05 0.4 TYP LRS1331 1.4 MAX. 72FBGA 25 ...
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... EUROPE SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Facsimile: (49) 40 2376-2232 http://www.sharpmed.com LRS1331 ASIA SHARP Corporation Integrated Circuits Group 2613-1 Ichinomoto-Cho Tenri-City, Nara, 632, Japan Phone: +81-743-65-1321 Facsimile: +81-743-65-1532 http://www.sharp.co.jp ...