s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 125
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s71jl064ha0bfw62
Manufacturer Part Number
s71jl064ha0bfw62
Description
Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
Manufacturer
Advanced Micro Devices
Datasheet
1.S71JL064HA0BFW62.pdf
(141 pages)
- Current page: 125 of 141
- Download datasheet (4Mb)
64 Mb pSRAM (supplier 3)
64 Megabit CMOS Pseudo Static SRAM
Features
Description
Pin Description
February 25, 2004 S71JLxxxHxx_00A1
The S71JL128HC0 contains a 67,108,864-bit, pseudo static random access mem-
ory (PSRAM) organized as 4,194,304 words by 16 bits. It provides high density,
high speed, and low power. The device operates on a single power supply. The
device also features SRAM-like W/R timing whereby the device is controlled by
DE1#, OE#, and WE# on asynchronous. The device has the page access opera-
tion. Page size is 8 words. The device also supports deep power-down mode,
realizing low-power standby.
A0 to A21
A0 to A2
I/O1 to I/O16
CE1#
CE2
WE#
OE#
VDD
GND
NC
LB#, UB#
Organized as 4,194,304 words by 16 bits
Single power supply voltage of 2.6 to 3.3 V
Direct TTL compatibility for all inputs and outputs
Deep power-down mode: Memory cell data invalid
Page operation mode:
— Page read operation by 8 words
Logic compatible with SRAM R/W (WE#) pin
Standby current
— Standby
— Deep power-down standby
Access Times:
— Access Time
— CE1# Access Time
— OE# Access Time
— Page Access Time
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P r e l i m i n a r y
64 Mb pSRAM (supplier 3)
Address Inputs
Page Address Inputs
Data Inputs/Outputs
Chip Enable Input
Chip select Input
Write Enable Input
Output Enable Input
Data Byte Control Inputs
Power
Ground
No Connection
100 µA
5 µA
70 ns
70 ns
25 ns
30 ns
113
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