s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 103

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

Block Diagram
Notes:
1. When UB# and LB# are in select mode (low), I/O
2. When the device is in standby mode, control inputs (WE#, OE#, UB#, and LB), address inputs and data input/
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the circuit.
4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally
110
CE1#
mode only I/O
If both UB# and LB# are in the deselect mode (high), the chip is in a standby mode regardless of the state of CE1#
or CE2.#
outputs are internally isolated from any external influence and disabled from exerting any influence externally.
isolated from any external influence.
H
X
L
L
L
L
Address
Inputs
A
0
- A
CE2
CE1#
19
X
H
H
H
H
WE#
L
OE#
UB#
LB#
CE2
0
- IO
WE#
H
H
X
X
X
L
7
are affected as shown. When UB is in the select mode only I/O
Control
Logic
Address
Decode
Logic
OE#
X
X
X
X
H
L
Figure 46. Functional Block Diagram
L
L
L
Table 21. Functional Description
UB#/LB#
(Note
(Note
(Note
X
X
H
16 Mb pSRAM (supplier 2)
3)
3)
3)
1024K x 16 bit
RAM Array
0
- I/O
P r e l i m i n a r y
I/O
Data Out
Data In
High Z
High Z
High Z
High Z
(Note
15
are affected as shown. When LB# only is in the select
1)
Standby
Standby
Standby
Write
MODE
Active
Read
(Note
(Note
(Note
(Note
Input/
Output
Mux and
Buffers
3)
8
2)
4)
4)
- I/O
Active -> Standby
Active -> Standby
15
S71JLxxxHxx_00A1 February 25, 2004
are affected as shown.
I/O
I/O
Standby
8
0
- I/O
- I/O
Standby
Standby
Standby
POWER
(Note
15
7
(Note
(Note
4)
4)
4)