s71jl064ha0bfw62 Advanced Micro Devices, s71jl064ha0bfw62 Datasheet - Page 112

• Manufacturer Part Number: s71jl064ha0bfw62
• Description: Stacked Multi-chip Product Mcp Flash Memory And Psram Cmos 3.0volt-only, Simultaneous Operation Flash Memories And Static Ram/pseudo-static Ram
• Manufacturer: Advanced Micro Devices

Timing Diagrams
Note: CE1# = OE# = V
100
Deep Power Down
Power Mode
Standby
Address
Data Out
Powe r
on
Powe r Up Sequence
CE2=VIH
IL
, CE2 = WE# = V
Table 20. Standby Mode Characteristics
Previous Data Valid
Figure 36. Read Cycle 1—Addressed Controlled
Memory Cell Data
Initial State
(Wait 200 µs)
Invalid
Valid
IH
Figure 35. State Diagram
, UB# and/or LB# = V
16 Mb pSRAM (supplier 4)
Deep Pow er Down Exit Sequence
t OH
P r e l i m i n a r y
CE1# = V IH or V IL ,
CE2=V IH
CE1# =V IL , CE2=V IH ,
UB# & LB# or/and LB# = V IL
t A A
Active
Standby Current (µA)
t RC
e
IL
100
10
CE2=V IH ,
CE1# =V IH or
UB#, LB# =V IH
t OH
CE2=V IL
Data Valid
Deep Powe r
Down Mode
Standby
Mode
Wait Time (µs)
CE2=V IL
S71JLxxxHxx_00A1 February 25, 2004
200
0