mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 36

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

MT90520
Data Sheet
4.0
Module Functional Descriptions
As shown in Figure 1, “MT90520 Block Diagram,” on page 1, the MT90520 consists of the following major
components: Microprocessor Interface Module, External Memory Interface Module, TDM Interface Module,
UTOPIA Interface Module, TX_SAR Module, RX_SAR Modules (consisting of the UDT RX_SAR, SDT RX_SAR,
and Data RX_SAR), the Clock Management Module, and the Test Interface (JTAG) Module. This section describes
each module in detail.
4.1
Microprocessor Interface
The microprocessor interface permits an external microcontroller to access registers and internal memories within
the MT90520 device. In addition, this interface provides the microcontroller with access to the external memory
(synchronous ZBT SRAM) connected to the MT90520 device.
The MT90520 microprocessor interface is compatible with both Intel and Motorola processors. The user selects the
mode of operation of the internal CPU block via the Intel/Motorola pin.
The synchronous microprocessor interface supports word (i.e., 16-bit) data accesses only. Although all
microprocessor accesses to the device are word-wide, CPU addressing of the MT90520 is on a byte-wide basis.
There is a 20-bit address bus between the microcontroller and the MT90520 interface, featuring address lines
CPU_ADD[20] to CPU_ADD[1]. The virtual CPU_ADD[0] bit would select between high and low bytes in a word.
The AEM (Access External Memory) pin is effectively address line CPU_ADD[21] (or any higher address line
selected by the user) and determines if the CPU is accessing the internal registers and memories of the MT90520
(AEM = ‘0’) or the external memory (AEM = ‘1’).
All registers within the MT90520 device are accessed (for reads or writes) with fixed low latency. However, there is
a variable delay between a CPU access and the successful completion of an access to a memory, whether internal
to the device, or within external memory. In order to reduce this latency, the MT90520 supports indirect accesses to
internal and external memory via indirection registers. The user can designate a memory address which is to be
written or read, along with the data to be written to that memory location, and then initiate an indirect memory
access. The CPU must then wait for the access to be completed by either polling a register bit (waiting for the ACC
bit within the High Address Indirection Command Register at byte address 0006h to be cleared) or, if the service
request was enabled, by waiting for an interrupt. Then, if the access was a read, the user can read the accessed
data from the Indirection Data Register located at byte address 0008h. More information about the timing of CPU
accesses can be found in Section 7.2.1 on page 150.
Interrupt signals from the various modules of the MT90520 are gated together within the microprocessor interface
module to produce a single interrupt request signal, IRQ, which is presented to the CPU. There is a status register
within the microprocessor interface module indicating which module of the MT90520 generated the interrupt
request. As well, the microprocessor interface module contains an interrupt enable register which may be
programmed by the user to enable or disable interrupt sources. Details regarding interrupt handling within the
MT90520 are given in Section 4.1.2.
4.1.1
Global Reset
During a hardware reset (when the RESET pin is driven low), the CPU-accessible registers of the MT90520 go to
their respective reset states, as indicated in the register descriptions of Section 6.2. At that time, the RESET bit in
the Chip Wide Reset Register (CWRR) at 0000h is set high, “latching” the reset state. No registers other than the
CWRR can be accessed until the RESET bit is cleared. The steps to reset and restart the MT90520 are therefore:
1. Assert hardware reset by driving the RESET pin low, or initiate a software reset by writing 0001h to the CWRR
at byte address 0000h.
2. After at least 100 ns, remove hardware reset.
3. After at least 2 µs, clear the CWRR (de-assert software reset).
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