mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 163

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

UTO_OUT_CLK
UTO_OUT_CLAV
ATM_ENBPHY
UTO_OUT_ENB
ATM_CLAVPHY
UTO_OUT_SOC
UTO_OUT_DATA[7:0
UTO_IN_CLK Period
UTO_IN_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
(UTO_IN_CLAVATM_ENBPHY,
UTO_IN_SOC asserted and UTO_IN_DATA[7:0]
VALID) to UTO_IN_CLK rising
Input Hold Time - UTO_IN_CLK rising to
(UTO_IN_DATA[7:0] INVALID and
UTO_IN_SOC, UTO_IN_CLAVATM_ENBPHY
de-asserted)
Output Delay - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY asserted
Output Hold Time - UTO_IN_CLK rising to
UTO_IN_ENBATM_CLAVPHY de-asserted
Table 100 - UTOPIA Level 1 Interface Timing - PHY mode - Incoming Data (UTOPIA TX Bus)
Figure 62 - UTOPIA Level 1 Interface Timing - ATM Mode - Outgoing Data (UTOPIA TX Bus)
Characteristic
t
UTXIS
t
UTX1P
t
UTXD
X
t
UTXH
H1
t
UTX1H/L
t
t
t
H2
Sym.
t
t
UTX1P
UTXIH
UTXIS
UTXD
UTXH
Zarlink Semiconductor Inc.
MT90520
H3
19.23
Min.
7.7
4
1
1
163
P44
t
UTX1P
Typ.
/2
P45
at least
4 cycles before the next cell
Max.
13.8
t
UTX1L
P46
Units
ns
ns
ns
ns
ns
ns
t
UTX1H
P47
UTO_IN_CLK = 52 MHz
C
C
L
L
=20 pF; UTO_IN_CLK < 52 MHz
=20 pF; UTO_IN_CLK < 52 MHz
t
UTXH
t
UTXH
P48
Test Conditions
X
Data Sheet
V
V
V
V
V
TT
TT
TT
TT
TT