mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 159

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Table 96 and Table 97 refer to output clock parameters which are displayed below in Figure 58, Figure 59, and
Figure 60.
SToCLK/C4M/C2M Clock Period
SToCLK/C4M/C2M Pulse Width (HIGH / LOW)
Note: In Generic format, both clock polarity and frame pulse polarity are programmable. Data can be sampled either on
the falling edge or the rising edge of the clock. The frame pulse can have either positive or negative polarity.
STiMF/F0
STiCLK or C4M/C2M
2.048 MHz
DSTi/CSTi
STiMF/F0
STiCLK or C4M/C2M
4.096 MHz
DSTi/CSTi
1.544 Mbps bus (1.544 MHz clock)
1.544 or 2.048 Mbps bus (2.048 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
1.544 Mbps bus (1.544 MHz clock)
1.544 or 2.048 Mbps bus (2.048 MHz clock)
2.048 Mbps bus (4.096 MHz clock)
Characteristic
Bit 0, Last
Channel
Table 96 - TDM Bus Output Clock Parameters
Bit 1, Last
Figure 56 - TDM Bus Inputs - Generic Bus Sampling
Channel
Figure 57 - TDM Bus Inputs - ST-BUS Sampling
t
FIS
Channel 0
Bit 7,
Zarlink Semiconductor Inc.
Bit 0, Last
Channel
t
FIH
MT90520
t
t
FIS
159
SIS
t
SToCKH/L
Channel 0
t
Sym.
SToCK
t
Bit 6,
SIS
Channel 0
t
Bit 7,
STiCK
t
t
SIH
FIH
Min.
t
STiCK
t
SIH
Typ.
Channel 0
648
488
244
324
244
122
Bit 5,
t
STiCKH
Channel 0
t
STiCKH
Bit 6,
Max.
t
STiCKL
t
STiCKL
Units
ns
ns
ns
ns
ns
ns
Channel 0
Bit 4,
Test Conditions
Data Sheet
V
V
V
TT
TT
TT
V
V
V
TT
TT
TT