mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 168

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

8.0
8.1
8.1.1
To prevent device latch-up, it is recommended to turn on the I/O power (3.3 V) first, followed by the core power (2.5
V). This can be done in one of two ways:
•
•
In general, the power-down sequence should be the reverse of the power-up sequence. Thus, the 2.5 V rail should
be turned off first, followed by the 3.3 V rail.
8.1.2
The MT90520 can interface with both the pipelined and flow-through types of synchronous static zero bus
turnaround (ZBT) RAM. The clock driving the external memory device must be the same as the clock which is fed
to the MT90520 at its MCLK input, as shown in Figure 67 below.
By powering up the 3.3 V rail first, preventing the 2.5 V rail from powering up until the 3.3 V rail is stable.
By placing a Schottky diode between the 3.3 V and 2.5 V power rails (connecting the anode to the 2.5 V rail
and the cathode to the 3.3 V rail).
Board-Level Applications
Applications
Power-Up and Power-Down Sequence
External Memory Interface Connections
MT90520
Figure 67 - External Memory Interface
mclk
Zarlink Semiconductor Inc.
MT90520
168
clk
SRAM
ZBT
Data Sheet