mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 164

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

UTO_OUT_CLK Period
UTO_OUT_CLK Pulse Width (HIGH / LOW)
Input Setup Time -
UTO_OUT_CLAVATM_ENBPHY asserted to
UTO_OUT_CLK rising
Input Hold Time - UTO_OUT_CLK rising to
UTO_OUT_CLAVATM_ENBPHY de-
asserted
Output Delay - UTO_OUT_CLK rising to
(UTO_OUT_DATA[7:0] VALID and
UTO_OUT_ENBATM_CLAVPHY and
UTO_OUT_SOC asserted)
Output Hold Time - UTO_OUT_CLK rising
to (UTO_OUT_DATA[7:0] INVALID and
UTO_OUT_ENBATM_CLAVPHY and
UTO_OUT_SOC de-asserted)
UTO_IN_CLK
UTO_IN_CLAVATM
_ENBPHY
UTO_IN_SOC
UTO_IN_DATA[7:0]
UTO_IN_ENBATM
_CLAVPHY
Table 101 - UTOPIA Level 1 Interface Timing - PHY mode - Outgoing Data (UTOPIA RX Bus)
Figure 63 - UTOPIA Level 1 Interface Timing - PHY Mode - Incoming Data (UTOPIA TX Bus)
Characteristic
t
UTXD
X
t
UTXIS
t
UTX1P
H1
t
UTXIH
t
URX1H/L
t
t
t
t
t
Sym.
URX1P
URXIH
URXIS
URXD
URXH
H2
4 cycles before the next cell
Zarlink Semiconductor Inc.
H3
19.23
MT90520
Min.
7.7
4
1
1
164
t
URX1P
P44
Typ.
/2
P45
Max.
13.8
t
UTX1H
P46
Units
ns
ns
ns
ns
ns
ns
t
UTXH
t
UTX1L
P47
UTO_OUT_CLK = 52 MHz
C
C
L
L
= 20 pF; UTO_OUT_CLK < 52 MHz
= 20 pF; UTO_OUT_CLK < 52 MHz
t
UTXIH
P48
Test Conditions
X
Data Sheet
H1
V
V
V
V
V
TT
TT
TT
TT
TT