mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 25

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

Ball Pin #
A15
B15
C14
D14
B14
A14
B13
A13
C4M/C2M_b
TDM_CLK
SEC_REF
SEC_LOS
Pin Name
PHY_CLK
PRI_REF
PRI_LOS
F0_b
I/O
I/O
I/O
O
O
O
O
I
I
CMOS PD /
CMOS PD /
3.3 V, 2 mA Output clock running at DS1/E1/ST-BUS line rate, used to
3.3 V, 2 mA If high, indicates to an external PLL that the primary reference
3.3 V, 2 mA Output clock running at DS1/E1/ST-BUS line rate, used to
3.3 V, 2 mA If high, indicates to an external PLL that the secondary
CMOS PD
CMOS PD
Table 5 - Clock Management Pins
24 mA
24 mA
3.3 V
3.3 V
3.3 V
3.3 V
Type
Zarlink Semiconductor Inc.
MT90520
Clock input from external PLL, operating at DS1/E1/ST-BUS
line rate.
PRS-traceable clock input (8 kHz reference clock or
19.44 MHz clock from PHY network layer).
- Backplane clock to be used when all 8 TDM ports are to have
the same input and output clock.
- TDM clock running at either 4.096 MHz or 2.048 MHz.
- Input in TDM backplane slave mode; output in TDM
backplane master mode.
- Frame pulse which delineates the 8 kHz frame boundary on
PCM input and output streams.
- In 2.048 Mbps ST-BUS applications, this is a negative-going
pulse straddling the frame boundary and lasting for one cycle
of the 4.096 MHz clock.
- In Generic bus applications, this signal may be a positive-
going or negative-going pulse following the frame boundary
and lasting for one bit cycle (i.e., one cycle of the 2.048 MHz
clock).
- Input in TDM backplane slave mode; output in TDM
backplane master mode.
provide a primary reference clock for an external PLL.
Note: This pin will still present a clock (derived from an internal
PLL) even if its source clock is experiencing an LOS condition.
Therefore, the PRI_LOS signal should be used to qualify the
quality of this clock.
clock has experienced an LOS condition.
provide a secondary reference clock for an external PLL.
reference clock has experienced an LOS condition.
25
Description
Data Sheet