mt90520 Zarlink Semiconductor, mt90520 Datasheet - Page 26

• Manufacturer Part Number: mt90520
• Description: 8-port Primary Rate Circuit Emulation Aal1 Sar
• Manufacturer: Zarlink Semiconductor

AB21, E6, E10, E14, E18, E21, F5,
AF16, AF13, AF11, AF9, AF7, AC7
AC23, AD18, AE16, AC14, AE12,
AD26, AE17, AE15, AE13, AE11,
AB22, AE3, AE26, AD17, AD15,
F22, J5, K22, N5, P22, U5, V22
AC10, AC8, AD6, AD25, AC16,
AD13, AB12, AE9, AD8, AF5,
AA5, AB6, AB9, AB13, AB17,
AE10, AC9, AF6
Ball Pin #
C13
A12
C20
B20
A21
D19
E19
Table 6 - Master Clock, Test and Power Pins
TEST_OUT
VDD_3.3V PWR
Pin Name
TEST_IN
RESET
MCLK
TRST
TMS
TDO
TCK
TDI
Zarlink Semiconductor Inc.
MT90520
I/O
O
O
I
I
I
I
I
I
I
26
Schmitt
CMOS
CMOS
CMOS
CMOS
CMOS
3.3 V,
3.3 V,
Type
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
3.3 V
4 mA
4 mA
PU
PU
PU
PU
Master Clock.
This signal drives the internal logic. The
same clock should be driven to the external
memory
Chip reset signal (active LOW).
Note that internal reset activity is
synchronous to MCLK; this signal is latched
internally and held, and MCLK must be
applied to bring the MT90520 out of reset.
The TRST pin (JTAG reset) should also be
asserted LOW during chip reset. Also see
RESET bit in Chip Wide Reset Register at
address 0000h.
JTAG Test Mode Select.
JTAG Test Clock.
JTAG Test Data In.
Should be pulled HIGH if boundary-scan not
in use.
JTAG Test Reset input (active LOW).
Should be asserted LOW on power-up and
during reset. Must be HIGH for JTAG
boundary-scan operation. Note: This pin has
an internal pull-up and must be pulled down
externally for normal operation.
JTAG Test Data Out.
Test input pins.
These pins must be grounded.
Test output pins.
These pins should be left unconnected.
Power for I/O logic (3.3 V).
Description
Data Sheet