wm8192cdw-v Wolfson Microelectronics plc, wm8192cdw-v Datasheet - Page 4

• Manufacturer Part Number: wm8192cdw-v
• Description: 8+8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8192
PIN DESCRIPTION
w
PIN
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
2
3
4
5
6
7
8
9
VRLC/VBIAS
RLC/ACYC
AGND2
DVDD1
DVDD2
AGND1
VSMP
DGND
MCLK
AVDD
NAME
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]
GINP
RINP
BINP
OEB
SEN
SCK
VRB
VRX
VRT
SDI
Analogue output
Analogue output
Analogue output
Analogue input
Analogue input
Analogue input
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Analogue I/O
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Digital input
Supply
Supply
Supply
Supply
Supply
Supply
TYPE
DESCRIPTION
Red channel input video.
Analogue ground (0V).
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if
used on every pixel. ACYC autocycles between R, G, B inputs.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Serial data input.
Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in two multiplexed formats as shown, under
the control of register bit MUXOP[1:0]
See ‘Output Formats’ description in Device Description section for further details.
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device
Description section for further details.
Analogue supply (5V). This must be operated at the same potential as DVDD1.
Analogue ground (0V).
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Blue channel input video.
Green channel input video.
d10
d11
d12
d13
d14
d15
d8
d9
A
8+8-bit
d0
d1
d2
d3
d4
d5
d6
d7
B
d12
d13
d14
d15
A
d10
d11
d8
d9
B
4+4+4+4-bit
d4
d5
d6
d7
C
PD Rev 4.1 July 2004
Production Data
d0
d1
d2
d3
D
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