wm8192cdw-v Wolfson Microelectronics plc, wm8192cdw-v Datasheet - Page 19

• Manufacturer Part Number: wm8192cdw-v
• Description: 8+8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8192
OPERATING MODES
Table 4 WM8192 Operating Modes
Notes:
1.
2.
w
MODE
1
2
3
4
5
6
In Monochrome mode, SetReg3 bits 7:6 determine which input is to be sampled.
For Colour Line-by-Line, set control bit LINEBYLINE. For input selection, refer to Table 4, Colour Selection
Description in Line-by-Line Mode.
Colour
Pixel-by-Pixel
Monochrome/
Colour
Line-by-Line
Fast
Monochrome/
Colour
Line-by-Line
Maximum
speed
Monochrome/
Colour
Line-by-Line
Slow Colour
Pixel-by-Pixel
Slow
Monochrome/
Colour
Line-by-Line
DESCRIPTION
Table 4 summarises the most commonly used modes, the clock waveforms required and the register
contents required for CDS and non-CDS operation.
AVAILABLE
CDS
Yes
Yes
Yes
Yes
Yes
No
1.5MSPS
1.5MSPS
SAMPLE
2MSPS
2MSPS
4MSPS
6MSPS
RATE
MAX
The 3 input channels
are sampled in
parallel. The signal is
then gain and offset
adjusted before being
multiplexed into a
single data stream
and converted by the
ADC, giving an output
data rate of 6MSPS
max.
As mode 1 except:
Only one input
channel at a time
is continuously
sampled.
Identical to mode 2
Identical to mode 2
Identical to mode 1
Identical to mode 2
DESCRIPTION
INTERFACE
SENSOR
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 6:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 6:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 3:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is 2:1
MCLK max
= 12MHz
MCLK:
VSMP
ratio is
2n:1, n
MCLK max
= 12MHz
MCLK:
VSMP
ratio is
2n:1, n
REQUIRE-
TIMING
MENTS
4
4
SetReg1:
03(hex)
SetReg1:
07(hex)
Identical to
mode 2 plus
SetReg3:
bits 5:4 must
be set to
0(hex)
CDS not
possible
Identical to
mode 1
Identical to
mode 2
CONTENTS
REGISTER
WITH CDS
PD Rev 4.1 July2004
Production Data
SetReg1:
01(hex)
SetReg1:
05(hex)
Identical to
mode 2
SetReg1:
45(hex)
Identical to
mode 1
Identical to
mode 2
CONTENTS
REGISTER
WITHOUT
CDS
19