wm8192cdw-v Wolfson Microelectronics plc, wm8192cdw-v Datasheet - Page 18

• Manufacturer Part Number: wm8192cdw-v
• Description: 8+8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8192
POWER MANAGEMENT
LINE-BY-LINE OPERATION
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Power management for the device is performed via the Control Interface. The device can be powered
on or off completely by setting the EN bit and SELD bit low. Alternatively, when control bit SELPD is
high, only blocks selected by further control bits (SELDIS[3:0]) are powered down. This allows the
user to optimise power dissipation in certain modes, or to define an intermediate standby mode to
allow a quicker recovery into a fully active state. In Line-by-line operation, the green and blue channel
PGAs are automatically powered down.
All the internal registers maintain their previously programmed value in power down modes and the
Control Interface inputs remain active. Table 2 summarises the power down control bit functions.
Table 2 Power Down Control
Certain linear sensors (e.g. Contact Image Sensors) give colour output on a line-by-line basis. i.e. a
full line of red pixels followed by a line of green pixels followed by a line of blue pixels. In order to
accommodate this type of signal the WM8192 can be set into Monochrome mode, with the input
channel switched by writing to control bits CHAN[1:0] between every line. Alternatively, the WM8192
can be placed into colour line-by-line mode by setting the LINEBYLINE control bit. When this bit is
set the green and blue processing channels are powered down and the device is forced internally to
only operate in MONO mode (because only one colour is sampled at a time) through the red channel.
Figure 17 shows the signal path when operating in colour line-by-line mode.
Figure 17 Signal Path When in Line-by-Line Mode
In this mode the input multiplexer and (optionally) the PGA/Offset register multiplexers can be auto-
cycled by the application of pulses to the RLC/ACYC input pin by setting the ACYCNRLC register bit.
See Figure 4 for detailed timing information. The multiplexers change on the first MCLK rising edge
after RLC/ACYC is taken high. A write to the auto-cycle reset register causes these multiplexers to
be reset; selecting the RINP pin and the RED offset/gain registers. Alternatively, all three
multiplexers can be controlled via the serial interface by writing to register bits INTM[1:0] to select the
desired colour. It is also possible for the input multiplexer to be controlled separately from the PGA
and Offset multiplexers. Table 3 describes all the multiplexer selection modes that are possible.
Table 3 Colour Selection Description in Line-by-Line Mode
GINP
FME
RINP
BINP
0
0
1
1
VRLC/VBIAS
EN
X
0
1
ACYCNRLC
RLC
RLC
RLC
RLC
DAC
CL
0
1
0
1
SELDPD
4
INPUT
MUX
0
0
1
Internal,
no force mux
Auto-cycling,
no force mux
Internal,
force mux
Auto-cycling,
force mux
R
CDS
S
V
Device completely powers down.
Device completely powers up.
Blocks with respective SELDIS[3:0] bit high are disabled.
S
NAME
TIMING CONTROL
VSMP
R
G
B
R
G
B
OFFSET
MUX
PGA
MUX
MCLK
8
Input mux, offset and gain registers determined by
internal register bits INTM1, INTM0.
Input mux, offset and gain registers auto-cycled, RINP
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers selected from internal register
bits INTM1, INTM0.
Input mux selected from internal register bits FM1, FM0;
Offset and gain registers auto-cycled, RED
OFFSET
DAC
GINP
BLUE
+
PGA
BINP
RED… on RLC/ACYC pulse.
8
I/P SIGNAL
POLARITY
ADJUST
DESCRIPTION
RINP… on RLC/ACYC pulse.
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WM8192
+
CONFIGURABLE
ADC
INTERFACE
BIT
16-
CONTROL
SERIAL
PD Rev 4.1 July 2004
PORT
DATA
I/O
Production Data
GREEN
OP[7:0]
SEN
SCK
SDI
RLC/ACYC
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