WM9705 Wolfson Microelectronics plc, WM9705 Datasheet

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WM9705

Manufacturer Part Number
WM9705
Description
Manufacturer
Wolfson Microelectronics plc
Datasheet

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DESCRIPTION
The WM9705 is a high-quality stereo audio codec with an
integrated touch screen controller.
The audio section is compliant with the Intel AC’97 Rev 2.2
specification. It performs full-duplex 18-bit codec functions and
supports variable sample rates from 8 to 48k samples/s with
high signal to noise ratio. Optional AC’97 features include 3D
sound
headphone
primary/secondary
Headphone auto-detect, I
mono output are included.
Additionally, the WM9705 integrates a complete 4-wire touch
screen controller, including on-chip screen drivers, pen-down
detection feature, and pressure measurement capability.
A 5-pin digital bi-directional AC-Link serial interface allows
transfer of control data and DAC and ADC words to and from
the AC’97 controller. The WM9705 is fully operable on 3V or 5V
or mixed 3/5V supplies, and is packaged in the industry
standard 48-pin TQFP package with 7mm body size, or in a
smaller 7 × 7 × 0.9mm QFN.
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
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AUXADC
LINEINR
LINEINL
CDGND
BMON
MIC2
MIC1
CDR
CDL
enhancement,
MIC SELECT
(Reg 20h)
M
U
X
headset autodetect
outputs,
AUX
VID
HPOUTL
M
U
X
MIC BOOST
(Reg 0Eh)
SWITCH MATRIX
TOUCH PANEL
mode
0/20
dB
hardware
line-level
2
S output and headphone buffer on the
DGND1
PHONE
Integrated Touch Screen Controller
PHONE
operation
AUX
4-wire resistive
touchpanel
PCBEEP
VID
Multimedia AC’97 CODEC with
DVDD1
PEN DOWN
at
sample
M
U
outputs,
X
http://www.wolfsonmicro.com/enews/
ADCSEL
CONTROL LOGIC
(Reg 1Ah)
RECORD
(Reg 1Ch)
SELECT
RECORD
GAIN
and
MICVOL (Reg 0Eh)
LINEINVOL (Reg 10h)
SAR
ADC
rate
stereo
S/PDIF
ADC
ADC
R
L
DGND2
conversion,
MODULATION
INTERFACE
RATE AUDIO
VARIABLE
FILTERS
DIGITAL
buffered
AC'97
DVDD2
output.
Σ ∆
CDVOL (Reg 12h)
DAC
DAC
L
R
W
24.576MHz
FEATURES
APPLICATIONS
WM9705
CLOCK
OSC
VID
(Reg 18h)
DACVOL
AC’97 rev2.2 compliant codec with pen digitiser
18-bit stereo audio codecs
On-chip sample rate conversion
Multiple channel input mixer
S/PDIF digital audio output
Headphone drivers on AUX and MONO outputs
4-wire touch screen interface with co-ordinate and
pressure measurement, and pen-down detection
Wake-up from sleep mode on pen down
3V to 5V operation
Extensive power management features including hardware
power down option
Standard AC’97 pinout in 48-lead TQFP package or
48-lead QFN package.
Personal Digital Assistants and ‘Smartphones’
PocketPC systems
AUX
(Reg 20h)
(Reg 0Ah)
POP
CX3D1 CX3D2
3D
(Reg 72h)
MIXVOL
Copyright ©2008 Wolfson Microelectronics plc
(Reg 0Ch)
VREF
Production Data, July 2008, Rev 4.5
M
U
X
(Reg 5Ch)
PSEL
MUX
HPGND
ADCNDAC
(Reg 5Ch)
(Reg 20h)
(Reg 5Ch)
WM9705
M
U
X
MIX
HPND
M
U
X
MASTER VOL
HPVDD
(Reg 02h)
MONO VOL
(Reg 04h)
(Reg 06h)
HPVOL
HPOUTL
HPOUTR
HPGND
LINEOUTL
LINEOUTR
MONO_OUT
(TX)
VREFOUT
16 / 32Ohm
headphone

Related parts for WM9705

WM9705 Summary of contents

Page 1

... A 5-pin digital bi-directional AC-Link serial interface allows transfer of control data and DAC and ADC words to and from the AC’97 controller. The WM9705 is fully operable mixed 3/5V supplies, and is packaged in the industry standard 48-pin TQFP package with 7mm body size smaller 7 × ...

Page 2

... WM9705 DESCRIPTION ............................................................................................................1 FEATURES..................................................................................................................1 APPLICATIONS ..........................................................................................................1 BLOCK DIAGRAM ......................................................................................................1 TABLE OF CONTENTS ..............................................................................................2 ORDERING INFORMATION .......................................................................................4 ABSOLUTE MAXIMUM RATINGS..............................................................................4 RECOMMENDED OPERATING CONDITIONS ..........................................................5 PIN CONFIGURATION................................................................................................6 PIN DESCRIPTION .....................................................................................................7 POWER CONSUMPTION .........................................................................................12 DETAILED TIMING DIAGRAMS ...............................................................................13 AC-LINK LOW POWER MODE .........................................................................................13 COLD RESET....................................................................................................................13 WARM RESET ..................................................................................................................14 CLOCK SPECIFICATIONS ...............................................................................................14 DATA SETUP AND HOLD (50PF EXTERNAL LOAD).......................................................15 SIGNAL RISE AND FALL TIMES ...

Page 3

... WM9705 PEN DIGITISER OPERATION ..................................................................................40 TIMING OF PEN DIGITISER OPERATIONS.....................................................................41 CONTROL OF PEN DIGITISER FUNCTIONS ..................................................................41 READBACK OF PEN DIGITISER RESULTS.....................................................................42 CONVERSION CONTROL ................................................................................................43 PRESSURE MEASUREMENT ..........................................................................................48 MASK FUNCTION .............................................................................................................49 STANDBY OPERATION AND WAKE-UP..........................................................................50 AUXILIARY CONVERSIONS.............................................................................................51 PACKAGE DIMENSIONS - TQFP.............................................................................53 PACKAGE DIMENSIONS - QFN...............................................................................54 IMPORTANT NOTICE ...............................................................................................55 ADDRESS: ........................................................................................................................55 w Production Data PD Rev 4.5 July 2008 ...

Page 4

... DEVICE RANGE o WM9705SEFL/V - WM9705SEFL/RV - Note: Reel quantity = 2,200 ABSOLUTE MAXIMUM RATINGS Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified ...

Page 5

... WM9705 RECOMMENDED OPERATING CONDITIONS PARAMETER Digital supply range Analogue supply range Digital ground Analogue ground Difference AGND to DGND – Note 1 Difference AVDD to DVDD – Note 2 Note: 1. AGND is normally the same as DGND and HPGND 2. AVDD should be greater than or equal to DVDD w SYMBOL TEST CONDITIONS ...

Page 6

... WM9705 PIN CONFIGURATION DVDD1 XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DVDD2 SYNC RESETB PCBEEP Figure 1 TQFP Pinout DVDD1 XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DVDD2 SYNC RESETB PCBEEP Figure 2 QFN Pinout ...

Page 7

... WM9705 PIN DESCRIPTION PIN 48 PIN QFN 48 PIN TQFP 1 DVDD1 DVDD1 2 XTLIN XTLIN 3 XTLOUT XTLOUT 4 DGND1 DGND1 SDATAOUT SDATAOUT 5 6 BITCLK BITCLK 7 DGND2 DGND2 8 SDATAIN SDATAIN 9 DVDD2 DVDD2 SYNC SYNC 10 11 RESETB RESETB 12 PCBEEP PCBEEP PHONE PHONE 13 14 X+/AUXL X+/AUXL 15 X-/AUXR ...

Page 8

... WM9705 Electrical characteristics Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, 48kHz audio sampling, T PARAMETER Digital Logic Levels (DVDD = 3.3V) Input LOW level Input HIGH level Output LOW Output HIGH Analogue Audio I/O Levels (Input Signals on any audio inputs, Outputs on LINEOUT L, R and MONO and HPOUT L,R) Input level ...

Page 9

... WM9705 Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, 48kHz audio sampling, T PARAMETER Mixer Inputs to Line-out (10kΩ load) Maximum input voltage Maximum output voltage Signal to Noise Ratio A-weighted (Note 2) Total Harmonic Distortion + Noise -1dBfs input Input impedance (CD inputs) Input impedance (other mixer inputs) Input impedance MIC inputs ...

Page 10

... WM9705 Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, MCLK = 24.576MHz, T PARAMETER PEN and AUXILIARY INPUT ADC Resolution Differential non-linearity error Integral non-linearity error Offset error Gain error Noise Conversion time Acquisition time Throughput rate Multiplexer settling time ADC positive reference ADC negative reference ADC sampling capacitance ...

Page 11

... WM9705 Figure 3 Distortion Versus Power on Headphone Outputs, using 32 Ω Load and AVDD = HPVDD = 3.3V w -100 -90 -80 -70 -60 -50 -40 Output Power (mW) - Production Data Rev 4.5 July 2008 11 ...

Page 12

... The same digital data is output to both slots. 2. The POP bit (reg 20h) also needs to be set for this mode. 3. These values are recorded with no external clocks applied to the WM9705. 4. Pen active duty cycle is approximately 10%. Average analogue current consumption is approximately 10% of stated figure. w ...

Page 13

... WM9705 DETAILED TIMING DIAGRAMS Test Characteristics: AVDD = 3.3V, DVDD = 3.3V, AGND = 0V …………..T All measurements are taken at 10% to 90% DVDD, unless otherwise stated. All the following timing information is guaranteed, not tested. AC-LINK LOW POWER MODE BITCLK SDATAOUT SDATAIN Figure 4 AC-Link Powerdown Timing ...

Page 14

... WM9705 WARM RESET BITCLK Figure 6 Warm Reset Timing SYNC active high pulse width SYNC inactive to BITCLK startup delay CLOCK SPECIFICATIONS BITCLK Figure 7 Clock Specifications (50pF External Load) PARAMETER BITCLK frequency BITCLK period BITCLK output jitter BITCLK high pulse width (Note 1) BITCLK low pulse width (Note 1) ...

Page 15

... Figure 9 Signal Rise and Fall Times (50pF External Load) Incoming signals (from the AC’97 controller to the WM9705) SDATAOUT rise time SDATAOUT fall time SYNC rise time SYNC fall time Outgoing signals (from the WM9705 to the AC’97 controller) BITCLK rise time BITCLK fall time SDATAIN rise time SDATAIN fall time w ...

Page 16

... It is highly recommended that the Intel AC’97 rev2.2 specification be studied in parallel with this document: This specification can be downloaded from the Intel web site. The WM9705 is fully operable mixed 3/5V supplies, and is packaged in the industry standard 48pin TQFP package with 7mm body size. ...

Page 17

... WM9705 NON - AC’97 FEATURES In addition to the AC’97 features offered, WM9705 also supports: 4-wire pen digitiser with integrated screen driver, featuring highly flexible modes of operation, supporting autonomous screen conversions, and auxiliary conversions. Screen X and Y connections driven from AUX and VID stereo input pins, which are still connected. ...

Page 18

... WM9705 Figure 10 Functional Block Diagram w Reg 14h b15 Reg 16h b15 Production Data PD Rev 4.5 July 2008 18 ...

Page 19

... X/Y screen connections are those that would normally be used for AUX and VID stereo inputs in a conventional AC ’97 codec. In WM9705 these pins remain connected to the MIXER and ADC inputs, and may be used as analogue inputs, with the restriction that gain through the mixer input is fixed at 0dB. The normal MUTE function is provided using bit 15 in the appropriate register recommended that these MUTE bits are left ‘ ...

Page 20

... BB80 2 S operation, provided a weak pull-up (circa 100k) was 2 S modes the data that is output may be sent from the WM9705 via the data are selected by bits SPSA[1:0] in register 2Ah. WM9705 is compliant 2 S data from the next data slots available after the audio data 2 S data: (further details in the register description section later) ...

Page 21

... PRIMARY/SECONDARY ID SUPPORT WM9705 supports operation as either a primary or a secondary codec. Configuration of the device as either a primary secondary, is selected by tying the CID0 pin 45 on the package. Fundamentally, a device identified as a primary ( CID0 = ‘hi’) produces BITCLK as an output, whereas a secondary (any other ID) must be provided with BITCLK as an input ...

Page 22

... WM9705 When a headphone is connected the low impedance to ground of the headset pulls down the DC level to near ground headset with microphone is plugged in, the high impedance of the microphone does not pull down the DC level on the tip connection, the DC on this pin now rising to near positive supply ...

Page 23

... Default values and functional behavior are further described in the Serial Interface Register Map description. DAC slot mapping defaults are in Table 2. AC-LINK DIGITAL SERIAL INTERFACE PROTOCOL A digital interface has been provided to control the WM9705 and transfer data to and from it. This serial interface is compatible with the Intel AC’97 specification. The main control interface functions are: • ...

Page 24

... If a slot is tagged invalid the responsibility of the source of the data, (the WM9705 for the input stream, AC’97 controller for the output stream), to stuff all bit positions with 0s during that slot’s active time. ...

Page 25

... In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97 controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s example, consider an 8-bit sample stream that is being played out to one of the WM9705’s DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12 bit positions, which are stuffed with 0s by the AC’ ...

Page 26

... Bit (18:12) Bit (11:0) The first bit (MSB) sampled by the WM9705 indicates whether the current control transaction is a read or write operation. The following 7 bit positions communicate the targeted control register address. The trailing 12 bit positions within the slot are reserved and must be stuffed with 0s by the AC’ ...

Page 27

... Within slot 0 the first bit is a global bit (SDATAIN slot 0, bit 15) which flags whether the WM9705 is in the Codec Ready state or not. If the Codec Ready bit this indicates that the WM9705 is not ready for normal operation. This condition is normal following the desertion of power on reset for example, while the WM9705’ ...

Page 28

... Bit (19:4) Bit (3:0) Table 6 Status Data Port Bit Assignments If slot 2 is tagged invalid by the WM9705, then the entire slot will be stuffed with 0s by the WM9705. SLOTS 3 AND 4: PCM RECORD LEFT AND RIGHT CHANNELS Audio input frame slots 3 and 4 are the left and right channel outputs of the WM9705’s audio ADC ...

Page 29

... Pen ADC data. SLOTS 10 AND 11: These data slots may be utilised by the WM9705 to output audio data under control of the mapping bits ASS[1:0] in register 5Ch, allowing implementation of multi-channel systems. These slots may also be used to output Pen ADC data. ...

Page 30

... BITCLK, SYNC is treated as an asynchronous input used in the generation of a warm reset to the WM9705. The WM9705 will not respond with the activation of BITCLK until SYNC has been sampled low again by the WM9705. This will preclude the false detection of a new audio frame. PEN DOWN WM9705 WAKE-UP ...

Page 31

... WM9705 Support for the MSB of the volume level is not provided by the WM9705. If the MSB is written to, then the WM9705 detects when that bit is set and sets all 4 LSBs to 1s. Example: If the driver writes a 1xxxxx the WM9705 interprets that as x11111. It will also respond when read with x11111 rather than 1xxxxx, the value written to it ...

Page 32

... LPBK 3D CONTROL REGISTER (INDEX 22h) This register is used to control the centre and/or depth of the 3D stereo enhancement function built into the AC’97 component. Only the depth bits DP0 to 3 have effect in the WM9705. Table 13 3D Control Register POWERDOWN CONTROL/STATUS REGISTER (INDEX 26h) This read/write register is used to program power-down states and monitor subsystem readiness ...

Page 33

... When the AC-link Codec Ready indicator bit (SDATAIN slot 0, bit 15 indicates that the AC-link and the WM9705 control and status registers are in a fully operational state. The AC’97 controller must further probe this Powerdown Control/Status Register to determine exactly which subsections, if any, are ready. Note that the normal default condition of WM9705 when RESETB is applied is ‘ ...

Page 34

... Figure 16 illustrates one example procedure complete Powerdown of the WM9705. From normal operation sequential writes to the Powerdown Register are performed to Powerdown the WM9705 a piece at a time. After everything has been shut off (PR0 to PR3 set), a final write (of PR4) can be executed to shut down the WM9705’s digital interface (AC-link). ...

Page 35

... PCM converters. Default is the 48ks/s rate. Note that only Revision 2.2 recommended rates are supported by the WM9705, selection of any other unsupported rates will cause the rate to default to the nearest supported rate, and the supported rate value to be latched and so read ...

Page 36

... SPDIF validity bit SPCV in register 2Ah should be read to ensure the desired configuration is valid. Only then should the SPDIF enable bit in register 2Ah be set. This ensures that control and status information start up correctly at the beginning of SPDIF transmission. WM9705 only supports an SPDIF sample rate of 48kHz. CONTROL ...

Page 37

... WM9705 CONTROL BIT AMUTE HSCP MPUEN MHPZ PSEL HSDT HSEN HPND AMEN ADCNDAC ADCO HPF HSCMP ASS1 ASS0 Table 21 Vendor Specific Control Register 5Ch AMUTE indicates automute state has been detected. This is a read-only bit automute detected. HSCP is a read only bit, indicating headset detected the output from the headset autodetect comparator ...

Page 38

... Plug and Play Vendor ID code. The first character of that F0, the second character S7 to S0, and the third T7 to T0. These three characters are ASCII encoded. The REV7 to REV0 field is for the Vendor Revision number. In the WM9705 the vendor ID is set to WML5. Wolfson is a registered Microsoft Plug and Play vendor. ...

Page 39

... WM9705 SERIAL INTERFACE REGISTER MAP The following table shows the function and address of the various control bits that are loaded and read through the serial interface. Reg Name D15 D14 D13 00h Reset X SE4 SE3 02h Master volume Mute X X 04h ...

Page 40

... WM9705 PEN DIGITISER OPERATION The pen digitiser function comprises a 12 bit successive approximation ADC, with a multi-channel input multiplexor to select which signal to convert, and a switching matrix to control driving of signals to the resistive touchscreen plates. A finite state machine is provided in order to control and sequence conversion operations. ...

Page 41

... Control of the digitiser functions is via control bits written into control registers via the AC link. The following table shows the name, function and location of the control bits for the pen digitser section of the WM9705. Address locations are chosen to avoid unexpected corruption of normal AC’97 audio codec operation, using mostly vendor specific addresses from the AC’97 adddress map ...

Page 42

... Readback may be performed either by reading from the read only register 7Ah via the AC link enabling SLOT mode (by writing SLEN = 1 in register 76h) where results are placed into the AC link data slots by WM9705, and sent back to the controller. The readback word contains the 12 bit data in the lsb locations, plus a 3 bit header in the next 3 bit locations, whose value corresponds to the channel that the data was converted from ...

Page 43

... BUSY flag clearly precludes use of the EAPD external amplifier power down bit, but as the WM9705 has integrated headphone amplifier with it’s own power down bit PR6 in register 26h, this should not be a problem. If BSEN is not set, then EAPD operates as normal) If SLOT method is enabled (SLEN bit in register 76h is set ‘ ...

Page 44

... WM9705 POLLING METHOD The polling method relies on the controller to instruct every operation, i.e. to send an instruction requesting every individual conversion specifically. A polled conversion is requested by writing POLL bit 15 in register 76h, along with the address of the channel to be converted. The channel to convert is identified by a 3-bit tag word ADR[2-0] written to the Pen control register 76h ...

Page 45

... WM9705 Different types of polled conversion with delay set frame) SYNC Poll = 1, Coord = 0, ADR = 001 ( 0x76 = 0x9000 ) = X Measurement Write to 0x76 SDOUT with 0x9000 POLL Screen Switch X / ADC mux mode ADC MODE DELAY PENDATA Coord = 1, ADR = 011 ( 0x76 = 0xB800 ) = X, Y and Pressure ...

Page 46

... WM9705 CONTINUOUS METHOD The continuous method of conversion allows for an autonomous free running operation of the digitiser, converting pen X,Y results and either pressure or AUX channels continuously at a pre- set rate. This removes from the controller the overhead associated with instructing which conversion to do next etc. Continuous conversion is enabled by setting the CTC bit in register 76h ...

Page 47

... WM9705 Different types of continuous conversion with delay set frames) CTC = 1, CC=11, Coord = 0, ADR = 001 ( 0x76 = 0x1700 ) = X Measurement every 64 AC Link Frames SYNC Conversion 1 ADC Mode DELAY CONVERT Pen Data CTC = 1, CC=00, Coord = 1, ADR = 000 ( 0x76 = 0x0C00 ) = X and Y Measurement every 512 AC Link Frames ...

Page 48

... WM9705 BUSY SIGNAL The BUSY signal is derived from the pen state machine and is an indication of the AUXADC being active on a conversion cycle. When an AUXADC conversion is requested BUSY will go high 61 BCLKs after the rising edge of SYNC in the frame that the conversion was requested. BUSY will remain high until the data from the conversion is written into register 7A as the state machine sees the register write as the last stage of the conversion ...

Page 49

... WM9705 MASK FUNCTION It is anticipated that sources of glitch noise such as LCD ‘invert’ signals will likely be picked up by the touchscreen plates and affect measurement accuracy. In order to minimise this effect, a signal may be applied to the MASK pin, which depending on the setting of the MSK[1-0] bits in register 78h, will delay the start of sampling of any input to the ADC ...

Page 50

... The AC link interface specification allows for standby operation, with all clocks stopped and the oscillator powered down, (all PR bits set). From this state, either the controller or the Codec can re-awaken the AC link. This feature is used by WM9705 to allow the standby operation, and wake on pen down function. ...

Page 51

... WM9705 Setting PRP[1: will power off the digitiser and and pen down detection. PENDET will not toggle on pen down. Provision of the PENDET flag as well as the the AC link wake up procedure allows controllers that might not be full AC link compliant to still operate in this way, by monitoring the change in state of PENDET and using that signal as a wake-up flag ...

Page 52

... MASTER MODE Direct battery measurement (6.5V max) LAYOUT NOTES C6, C20, C23 and C24 should be placed as close as possible to the relevant WM9705 connecting pin as possible. 2. AGND and GND should be connected as close as possible to the WM9705. 3. For added strength and heat dissipation recommended that GND_PADDLE (pin 49) is connected to AGND ...

Page 53

... WM9705 PACKAGE DIMENSIONS - TQFP FT: 48 PIN TQFP ( 1.0 mm Dimensions Symbols (mm) MIN NOM A ----- ----- A 0.05 ----- 1 A 0.95 1. 0.17 0.22 c 0.09 ----- D 9.00 BSC D 7.00 BSC 1 E 9.00 BSC E 7.00 BSC 1 e 0.50 BSC L 0.45 0. 3.5 Θ Tolerances of Form and Position ccc 0.08 REF: JEDEC.95, MS-026 NOTES: A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS. ...

Page 54

... WM9705 PACKAGE DIMENSIONS - QFN FL: 48 PIN QFN PLASTIC PACKAGE EXPOSED 6 GROUND PADDLE BOTTOM VIEW (A3) SIDE VIEW C SEATING PLANE W (A3 Exposed lead Half etch tie bar DETAIL 3 Symbols Dimensions (mm) MIN NOM A 0.80 0. 0.02 A3 0.20 REF b 0.18 0.25 D 7.00 BSC D2 5.00 5.15 E 7.00 BSC E2 5 ...

Page 55

... WM9705 IMPORTANT NOTICE Wolfson Microelectronics plc (“Wolfson”) products and services are sold subject to Wolfson’s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. Wolfson warrants performance of its products to the specifications in effect at the date of shipment. Wolfson reserves the right to make changes to its products and specifications or to discontinue any product or service without notice ...

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