wm8192cdw-v Wolfson Microelectronics plc, wm8192cdw-v Datasheet - Page 15

• Manufacturer Part Number: wm8192cdw-v
• Description: 8+8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8192
OUTPUT FORMATS
w
OFFSET DAC BLOCK: OFFSET (BLACK-LEVEL) ADJUST
The resultant signal V
PGA NODE: GAIN ADJUST
The signal is then multiplied by the PGA gain,
ADC BLOCK: ANALOGUE-DIGITAL CONVERSION
The analogue signal is then converted to a 16-bit unsigned number, with input range configured by
PGAFS[1:0].
where the ADC full-scale range, V
OUTPUT INVERT BLOCK: POLARITY ADJUST
The polarity of the digital output may be inverted by control bit INVOP.
The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by
setting control bit MUXOP[1:0]. Latency of valid output data with respect to VSMP is programmable
by writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing
Diagrams section.
Figure 12 shows the output data formats for Modes 1 – 2 and 4 – 6. Figure 13 shows the output data
formats for Mode 3. Table 1 summarises the output data obtained for each format.
Table 1 Details of Output Data Shown in Figure 12 and Figure 13.
Figure 12 Output Data Formats
4+4+4+4-bit
multiplexed
FORMAT
OUTPUT
(nibble)
8+8-bit
4+4+4+4-BIT
OUTPUT
OUTPUT
V
V
D
D
D
D
D
8+8-BIT
MCLK
2
3
1
1
1
2
2
(Modes 1
[15:0] = INT{ (V
[15:0] = INT{ (V
[15:0] = INT{ (V
[15:0] = D
[15:0] = 61535 – D
=
=
MUXOP[1:0]
00, 01, 10
1
1
A
[15:0]
is added to the Offset DAC output.
11
2, 4
A
V
V
B
1
2
3
3
3
+ {260mV
/V
/V
/V
6)
208/(283- PGA[7:0]) .............................................. Eqn. 5
C
1
FS
FS
FS
[15:0]
B
) 65535} + 32767 PGAFS[1:0] = 00 or 01 ...... Eqn. 6
) 65535}
) 65535} + 65535 PGAFS[1:0] = 10 ............... Eqn. 8
FS
D
OUTPUT
= 3V
OP[7:0]
OP[7:4]
PINS
(DAC[7:0]-127.5) } / 127.5 ..................... Eqn. 4
A = d15, d14, d13, d12, d11, d10, d9, d8
B = d7, d6, d5, d4, d3, d2, d1,d0
A = d15, d14, d13, d12
B = d11, d10, d9, d8
C = d7, d6, d5, d4
D = d3, d2, d1, d0
Figure 13 Output Data Formats
PGAFS[1:0] = 11 ............... Eqn. 7
(INVOP = 0) ...................... Eqn. 9
(INVOP = 1) ...................... Eqn. 10
4+4+4+4-BIT
(Mode 3)
OUTPUT
OUTPUT
8+8-BIT
MCLK
OUTPUT
A B
PD Rev 4.1 July2004
A
A B
Production Data
C D
B
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