wm8192cdw-v Wolfson Microelectronics plc, wm8192cdw-v Datasheet - Page 14

• Manufacturer Part Number: wm8192cdw-v
• Description: 8+8 Bit Output 16-bit Cis/ccd Afe/digitiser
• Manufacturer: Wolfson Microelectronics plc

WM8192
OVERALL SIGNAL FLOW SUMMARY
CALCULATING OUTPUT FOR ANY GIVEN INPUT
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Figure 11 represents the processing of the video signal through the WM8192.
Figure 11 Overall Signal Flow
The INPUT SAMPLING BLOCK produces an effective input voltage V
difference between the input video level V
difference between the input video level V
optionally set via the RLC DAC.
The OFFSET DAC BLOCK then adds the amount of fine offset adjustment required to move the
black level of the input signal towards 0V, producing V
The PGA BLOCK then amplifies the white level of the input signal to maximise the ADC range,
outputting voltage V
The ADC BLOCK then converts the analogue signal, V
The digital output is then inverted, if required, through the OUTPUT INVERT BLOCK to produce D
The following equations describe the processing of the video and reset level signals through
the WM8199. The values of V
setup. The PGA value is written first to set the input Voltage range, the Offset DAC is then
adjusted to compensate for any Black/Reset level offsets and finally the RLC DAC value is
set to position the rest level correctly during operation.
Note: Refer to the WAN0123 for detailed information on device calibration procedures.
INPUT SAMPLING BLOCK: INPUT SAMPLING AND REFERENCING
If CDS = 1, (i.e. CDS operation) the previously sampled reset level, V
input video.
If CDS = 0, (non-CDS operation) the simultaneously sampled voltage on pin VRLC is subtracted
instead.
If RLCEXT = 1, V
If RLCEXT = 0, V
V
RLCSTEP
V
V
V
RLCEXT=1
IN
RESET
VRLC
is the step size of the RLC DAC and V
CDS = 0
V
V
V
CDS = 1
1
1
VRLC
DAC
RLC
SAMPLING
RLCEXT=0
VRLC
VRLC
=
=
=
BLOCK
INPUT
+
See parametrics for
DAC voltages.
3
.
is an externally applied voltage on pin VRLC/VBIAS.
is the output from the internal RLC DAC.
-
V
V
V
(V
1
OFFSET DAC
IN
IN
RLCSTEP
BLOCK
+ +
- V
- V
1
Offset
DAC
V
RESET
VRLC
2
A = 208/(283-PGA[7:0])
V
and V
260mV*(DAC[7:0]-127.5)/127.5
2
RLCV[3:0]) + V
.................................................................... Eqn. 2
................................................................... Eqn. 1
BLOCK
PGA
PGA gain
X
3
IN
are often calculated in reverse order during device
and the input reset level V
V
IN
3
analog
RLCBOT
and the voltage on the VRLC/VBIAS pin, V
RLCBOT
2
+32768 if PGAFS[1:0]=0x
is the minimum output of the RLC DAC.
+0
+65535 if PGAFS[1:0]=10
.
3
, to a 16-bit unsigned digital output, D
x (65535/V
................................. Eqn. 3
if PGAFS[1:0]=11
ADC BLOCK
FS
V
V
VRLC is voltage applied to VRLC pin
CDS, RLCEXT,RLCV[3:0], DAC[7:0],
PGA[7:0], PGAFS[1:0] and INVOP are set
by programming internal control registers.
CDS=1 for CDS, 0 for non-CDS
)
IN
RESET
is RINP or GINP or BINP
RESET
RESET
is V
D
IN
digital
. For non-CDS this is the
D2 = D1 if INVOP = 0
D2 = 65535-D1 if INVOP = 1
1
1
sampled during reset clamp
. For CDS, this is the
, is subtracted from the
PD Rev 4.1 July 2004
OUTPUT
INVERT
BLOCK
Production Data
D
OP[7:0]
2
1
.
VRLC
2.
14
,