ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 85

• Manufacturer Part Number: ak4648
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

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MS0625-E-01
Addr
00H
Register Definitions
PMADL: MIC-Amp Lch and ADC Lch Power Management
PMDAC: DAC Power Management
PMLO: Stereo Line Out Power Management
PMSPL: Speaker-Amp Lch Power Management
PMMIN: MIN Input Power Management
PMVCM: VCOM Power Management
PMSPR: Speaker-Amp Rch Power Management
Each block can be powered-down respectively by writing “0” to each bit of this address. When the PDN pin is “L”, all
blocks are powered-down regardless as setting of this address. In this case, register is initialized to the default value.
When all power management bits are “0” in the 00H, 01H, 02H, 10H and 20H addresses and MCKO bit is “0”, all
blocks are powered-down. The register values remain unchanged.
When neither ADC nor DAC are powered-up, external clocks may not be present. When ADC or DAC is powered-up,
external clocks must always be present.
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
0: Power down (default)
1: Power up
Register Name
Power Management 1
PMMIN or PMAINL3 bit should be set to “1” for playback.
When the PMADL or PMADR bit is changed from “0” to “1”, the initialization cycle (1059/fs=24ms
@44.1kHz) starts. After initializing, digital data of the ADC is output.
When any blocks are powered-up, the PMVCM bit must be set to “1”. PMVCM bit can be set to “0” only
when all power management bits of 00H, 01H, 02H, 10H, 20H and MCKO bits are “0”.
Default
R/W
PMSPR
R/W
D7
0
PMVCM
R/W
D6
0
PMMIN
- 85 -
R/W
D5
0
PMSPL
R/W
D4
0
PMLO
R/W
D3
0
PMDAC
R/W
D2
0
RD
D1
0
0
[AK4648]
PMADL
2007/06
R/W
D0
0