ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 110

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ak4648

Manufacturer Part Number
ak4648
Description
Stereo Codec With Mic/hp/spk-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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MS0625-E-01
(11) Power Up of DAC, MIN-Amp and Speaker-Amp:
(12) Exit the power-save-mode of Speaker-Amp: SPPSN bit = “0” → “1”
(13) Enter the power-save-mode of Speaker-Amp : SPPSN bit = “1” → “0”
(14) Disable the path of “DAC
(15) Power Down DAC, MIN-Amp and Speaker-Amp: PMDAC = PMMIN = PMSPL = PMSPR bits = “1” → “0”
The DAC enters an initialization cycle when the PMDAC bit is changed from “0” to “1” at PMADL and
PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the initialization
cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”. The DAC
output reflects the digital input data after the initialization cycle is complete. When PMADL or PMADR bit is
“1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable (ALC gain is set by
IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the initialization cycle, ALC
operation starts from the gain set by IVL/R7-0 bits.
The powered-down channel is Hi-Z in Mono SPK Mode.
a.
b. Stereo SPK Mode or High Power Mono SPK Mode: PMDAC = PMMIN = PMSPL = PMSPR bits = “0”
Mono SPK Mode (When Lch Speaker-Amp, SPLP/SPLN pins are used.): PMDAC = PMMIN = PMSPL
bits = “0” → “1”
→ “1”
SPK-Amp”: DACS bit = “1”
- 110 -
“0”
[AK4648]
2007/06

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