ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 24

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ak4648

Manufacturer Part Number
ak4648
Description
Stereo Codec With Mic/hp/spk-amp
Manufacturer
AKM Semiconductor, Inc.
Datasheet

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Parameter
Control Interface Timing (I
Power-down & Reset Timing
Note 49. I
Note 50. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 51. AK4648 can be reset by the PDN pin = “L”.
Note 52. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
MS0625-E-01
SCL Clock Frequency
Bus Free Time Between Transmissions
Start Condition Hold Time (prior to first clock pulse)
Clock Low Time
Clock High Time
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling (Note 50)
SDA Setup Time from SCL Rising
Rise Time of Both SDA and SCL Lines
Fall Time of Both SDA and SCL Lines
Setup Time for Stop Condition
Capacitive Load on Bus
Pulse Width of Spike Noise Suppressed by Input Filter
PDN Pulse Width (Note 51)
PMADL or PMADR “↑” to SDTO valid (Note 52)
2
C is a registered trademark of Philips Semiconductors.
2
C Bus):
- 24 -
tHD:DAT
tHD:STA
tSU:DAT
tSU:STA
tSU:STO
Symbol
tHIGH
tLOW
tBUF
tPDV
fSCL
tPD
tSP
Cb
tR
tF
min
150
1.3
0.6
0.1
0.6
0.6
1.3
0.6
0
0
-
-
-
-
-
1059
typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
max
400
400
0.3
0.3
50
-
-
-
-
-
-
-
-
-
-
[AK4648]
2007/06
Units
kHz
1/fs
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
pF
ns
ns

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