ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 53

• Manufacturer Part Number: ak4648
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

3. Example of ALC Operation
Table 34 shows the examples of the ALC setting for MIC recording.
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
MS0625-E-01
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
REF7-0
IVL7-0,
IVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN and RFST1-0 bits
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
WR (ZTM1-0, WTM2-0, RFST1-0)
WR (RGAIN1, LMTH1)
Comment
Limiter detection Level
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
*WTM2-0 bits should be the same or
Maximum gain at recovery operation
Gain of IVOL
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
WR (IVL/R7-0)
ALC Operation
longer data as ZTM1-0 bits.
Manual Mode
WR (REF7-0)
Note : WR : Write
Figure 35. Registers set-up sequence at ALC operation
* The value of IVOL should be
the same or smaller than REF’s
Table 34. Example of the ALC setting
- 53 -
Data
E1H
E1H
001
01
01
00
00
00
0
1
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
fs=8kHz
− 4.1dBFS
Operation
4 times
Enable
+30dB
+30dB
Enable
1 step
1 step
32ms
32ms
(1) Addr=06H, Data=14H
(3) Addr=09H&0CH, Data=E1H
(2) Addr=08H, Data=E1H
(4) Addr=0BH, Data=00H
(5) Addr=07H, Data=21H
Data
E1H
E1H
011
01
11
00
00
00
0
1
fs=44.1kHz
− 4.1dBFS
Operation
23.2ms
23.2ms
4 times
Enable
Enable
+30dB
+30dB
1 step
1 step
[AK4648]
2007/06