ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 104

• Manufacturer Part Number: ak4648
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

MS0625-E-01
Power Supply
Internal Clock
PMVCM bit
(Addr:00H, D6)
(Addr:01H, D0)
2. PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
<Example>
LRCK pin
BICK pin
PDN pin
(1) After Power Up, PDN pin = “L”
(2) DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
(5) Normal operation stats after that the PLL is locked.
supplied. PLL lock time is 160ms(max.) when LRCK is a PLL reference clock. And PLL lock time is
2ms(max.) when BICK is a PLL reference clock.
VCOM should first be powered up before the other block operates.
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
(1)
(2)
(3)
Figure 72. Clock Set Up Sequence (2)
“H”. “L” time of 150ns or more is needed to reset the AK4648.
Input
(4)
“1”
- 104 -
(5)
4fs of
(1) Power Supply & PDN pin = “L”
Example:
Audio I/F Format: MSB justified (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
(2) Addr:04H, Data:32H
(3) Addr:00H, Data:40H
(4) Addr:01H, Data:01H
Addr:05H, Data:27H
[AK4648]
“H”
2007/06