ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 105

• Manufacturer Part Number: ak4648
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

MS0625-E-01
Power Supply
PMVCM bit
(Addr:00H, D6)
(Addr:01H, D1)
(Addr:01H, D0)
PMPLL bit
MCKO pin
3. PLL Slave Mode (MCKI pin)
<Example>
MCKO bit
LRCK pin
MCKI pin
BICK pin
PDN pin
(1) After Power Up, PDN pin = “L”
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0”
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
(6) The normal clock is output from MCKO during this period.
(7) The invalid frequency is output from MCKO after PLL is locked.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
PLL lock time is 40ms(max.).
The AK4648 should be operated as the recommended power-up/down sequence shown in “System Design
(Grounding and Power Supply Decoupling)” to avoid the pop noise at the speaker output, lineout output, and
headphone output.
VCOM should first be powered up before the other block operates.
(1)
(2)
(3)
(4)
(5)
40msec(max)
Figure 73. Clock Set Up Sequence (3)
(7)
“H”. “L” time of 150ns or more is needed to reset the AK4648.
Input
“1”
(6)
(8)
- 105 -
Output
Input
Example:
(1) Power Supply & PDN pin = “L”
Input Master Clock Select at PLL Mode: 11.2896MHz
BICK frequency at Master Mode: 64fs
Audio I/F Format: MSB justified (ADC & DAC)
Sampling Frequency: 44.1kHz
MCKO: Enable
BICK and LRCK input start
(2)Addr:04H, Data:4AH
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
Addr:05H, Data:27H
[AK4648]
“H”
2007/06