ak4648 AKM Semiconductor, Inc., ak4648 Datasheet - Page 112

• Manufacturer Part Number: ak4648
• Description: Stereo Codec With Mic/hp/spk-amp
• Manufacturer: AKM Semiconductor, Inc.

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MS0625-E-01
(Addr:05H, D5&D2-0)
(Addr:09H&0CH, D7-0)
(Addr:0AH&0DH, D7-0)
PMHPL/R/C bits
(Addr:01H, D5-4&D2)
DVL/R7-0 bits
HPG3-0 bits
IVL/R7-0 bits
(Addr: 0EH, D2)
HPL/R pins,
(Addr:0FH, D7-4)
(Addr:0FH, D0)
(Addr:01H, D6)
Headphone-amp Output
(Addr:00H, D2)
(Addr:00H, D5)
<Example>
HPMTN bit
PMDAC bit
PMMIN bit
HVCM pin
DACH bit
FS3-0 bits
FBEQ bit
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4648 is PLL mode, DAC and Speaker-Amp should be
(2) Set up the path of “DAC
(3) Enable 5-band Equalizer. (Boost amount is selected by Addr=25H-27H.): FBEQ bit = “0”
(4) Set up input volume (Addr: 09H and 0CH)
(5) Set up the output digital volume (Addr: 0AH and 0DH)
(6) Power up DAC and MIN-Amp: PMDAC = PMMIN bits = “0” → “1”
(7) Power up headphone-amp:
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
When PMADL = PMADR bits = “0”, IVL7-0 and IVR7-0 bits should be set to “91H”(0dB).
powered-up in consideration of PLL lock time after a sampling frequency is changed.
a.
b. Single-ended Mode: PMHPL=PMHPR bits = “0”
Set up analog volume for HP-Amp (Addr: 0F, HPG3-0 bits)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
The DAC enters an initialization cycle that starts when the PMDAC bit is changed from “0” to “1” at PMADL
and PMADR bits are “0”. The initialization cycle time is 1059/fs=24ms@fs=44.1kHz. During the
initialization cycle, the DAC input digital data of both channels are internally forced to a 2's complement, “0”.
The DAC output reflects the digital input data after the initialization cycle is complete. When PMADL or
PMADR bit is “1”, the DAC does not require an initialization cycle. When ALC bit is “1”, ALC is disable
(ALC gain is set by IVL/R7-0 bits) during an initialization cycle (1059/fs=24ms@fs=44.1kHz). After the
initialization cycle, ALC operation starts from the gain set by IVL/R7-0 bits.
Output voltages of headphone-amp are still VSS2.
The rise time depends on HVDD and the capacitor value connected with the MUTET pin. When HVDD=3.3V
and the capacitor value is 1.0 μ F ± 30%, the time constant (0.8 x HVDD/2) is
In Single-ended Mode, HVCM pin still outputs VSS2.
Pseudo Cap-less Mode: PMHPL = PMHPR = PMHPC bits = “0” → “1”
1011
0,000
E1H
18H
0
(1)
(2)
(3)
(4)
(5)
Figure 79. Headphone-Amp Output Sequence
(6)
HP-Amp”: DACH bit = “0” → “1”
(7)
(8)
Normal Output
1,111
1
1010
91H
28H
- 112 -
(9)
(10)
(11)
(12)
0
(13)
“1”
E x a m p le :
P L L M a s te r M o d e
S a m p lin g F r e q u e n c y : 4 4 .1 k H z
D V O L C b it = “ 1 ” ( d e fa u lt)
D ig ita l V o lu m e L e v e l: − 8 d B , H P V o lu m e L e v e l: - 3 d B
E Q : E n a b le
D e - e m p h a s e s r e s p o n s e : O F F
S o f t M u te T im e : 2 5 6 /fs , P s e u d o C a p -le s s M o d e
( 1 ) A d d r :0 5 H , D a t a :2 7 H
( 2 ) A d d r :0 F H , D a ta A 9 H
( 3 ) A d d r :0 E H , D a t a 1 5 H
( 4 ) A d d r :0 9 H & 0 C H , D a ta 9 1 H
( 5 ) A d d r :0 A H & 0 D H , D a ta 2 8 H
( 6 ) A d d r :0 0 H , D a t a 6 4 H
( 7 ) A d d r :0 1 H , D a t a 3 D H
( 8 ) A d d r :0 1 H , D a t a 7 9 H
( 9 ) A d d r :0 1 H , D a t a 3 9 H
( 1 0 ) A d d r :0 1 H , D a ta 0 9 H
( 1 1 ) A d d r :0 0 H , D a ta 4 0 H
( 1 2 ) A d d r :0 E H , D a ta 1 1 H
( 1 3 ) A d d r :0 F H , D a ta A 8 H
P la y b a c k
τ
r
= 120ms(typ.), 210ms(max.).
“1”
[AK4648]
2007/06