pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 58

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pt7a6525

Manufacturer Part Number
pt7a6525
Description
Pt7a6525/6525l/6526 Hdlc Controller
Manufacturer
Pericom Technology Inc
Datasheet

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• Microprocessor Interface Timing in Bus Mode
Note: If DACKA/B is provide by the DMA controller, the CS and DS is not needed to cause the falling of the
PT0017(12/05)
Figure 22. Diagram of Microprocessor Interface Timing in Intel Bus Mode (in Read Cycle)
Figure 23. Diagram of Microprocessor Interface Timing in Intel Bus Mode (in Write Cycle)
DRQR signal. Refer to Page 7, Table 2, the description of DACKA and DACKB.
CS x WR
D0 - D7
D0 - D7
CS x RD
DRQT
DRQR
High Impedance
t
RD
t
DRH
t
t
t
WW
DRH
RR
t
DW
Data
Data
58
PT7A6525/6525L/6526 HDLC Controller
t
DF
t
WD
t
t
WI
RI
High Impedance
Data Sheet
Ver:8

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