pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 19

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Data Transfer Modes
For both transmit and receive directions, data transfer between
the system memory and the PT7A6526 is controlled by either
Interrupts (Interrupt Mode) or by independent microprocessor
interaction using the device’s 4-channel DMA interface (DMA
Mode).
After RESET, the device operates in Interrupt Mode where data
transfer must be done by the microprocessor. The user selects
the DMA Mode by setting the DMA bit in the XBCH register.
Both channels can be independently operated in either Interrupt
or DMA Mode (e.g. Channel A-DMA, Channel B-Interrupt).
Interrupt Interface
Certain events within the device are indicated by means of a
single interrupt output that requests the microprocessor to read
status information from it. If Interrupt Mode is selected, data is
transferred from/to the device.
Since only one INT request output is provided, the cause of
each interrupt must be determined by the microprocessor by
reading the device`s interrupt status registers (ISTA, EXIR).
The structure of these registers is shown in Figure 7.
PT0017(12/05)
Figure 7. Interrupt Status Register
Bit
ISTA
EXIR
XMR
RME
7
RPF
XDU
6
RSC
PCE
5
XPR
Channel A
RFO
4
CSC
TIN
3
RFS
2
-
1
-
-
0
-
-
19
PT7A6525/6525L/6526 HDLC Controller
Five interrupt indications can be read directly from the ISTA
register and another six interrupt indications from the extended
interrupt register (EXIR).
After the PT7A6525/6525L requests an interrupt by setting its
INT pin to low, the microprocessor must first read the interrupt
status register of channel B(ISTA-B) in the associated interrupt
service routine. The three lowest order bits (bit 2-0) of ISTA-B
(ICA, EXA,EXB) point are sent to those registers in which the
actual interrupt source is indicated. The other bits of ISTA-B
indicate that there is an interrupt source from Channel B;
therefore, these bits also must always be checked. It is possible
that several interrupt sources are indicated as referring to one
interrupt request (e.g. if the ICA bit is set, at least one interrupt
is indicated in the ISTA register of channel A). See Register
Description for details.
The INT pin of the device remains active until all interrupt
sources are cleared by reading the corresponding interrupt
registers. Therefore it is possible that the INT pin is still active
when the interrupt service routine is finished.
The interrupt sources can be logically grouped as follows:
The interrupt indication of each ISTA register can be selectively
masked by setting the corresponding bit in the MASK register.
Bit
- receive interrupts: RPF, RME, RFO, RFS;
- transmit interrupts: XPR, XMR, XDU;
- special condition interrupts: RSC, PCE, TIN, CSC.
XMR
RME
7
XDU
RPF
6
RSC
PCE
5
XPR
RFO
Interrupt
Channel B
4
CSC
TIN
3
ICA
RFS
2
Data Sheet
EXA
1
-
EXB
0
-
Ver:8