pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 28

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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All frames exceeding this length are treated as if they have been
aborted from the opposite station, i.e., the microprocessor is
informed via a
- RME interrupt, and the
- RAB bit in RSTA register is set.
To distinguish the over-length frames from those really aborted
from the opposite station, the receive byte count (readable from
RBCH, RBCL registers) exceeds the maximum receive length
(via RL6...RL0) by one or two bytes in this case.
The check includes all data that are copied into the RFIFO. It
does not include the address byte (s) if address recognition is
selected. It includes the RSTA value in all operation mode.
One Bit Insertion
Similar to the zero bit insertion (bit-stuffing) as defined by the
HDLC protocol, the device offers a completely new feature of
inserting/deleting a one after seven consecutive zeros in the
PT0017(12/05)
Table 8. RESET Values
R
R
R
R
R
M
C
X
R
X
R
e
e
e
e
e
C
C
S
E
S I
g s
g s
g s
g s
g s
M
B
T
B
C
C
C
O
C
X
A
T
C
C
C
C
t s i
t s i
t s i
t s i
t s i
R
D
R
D
R I
A
R
H
H
R
R
2
1
E
R
r e
r e
r e
r e
r e
R
R
R
R
R
V
E
E
E
E
E
0 0
0 0
0 0
8 4
0 0
0 0
0 0
0 0
l a
S
S
S
S
S
H
H
H
H
H
H
H
H
e u
E
E
E
E
E
T
T
T
T
T
1
- 1
-
-
-
r -
-
-
-
-
R
A
x e
R
K
X
R
N
N
o p
s
c
T
C
T
N
n i
u f
a c
y b
c e
t u
F
o
o
i b
r e t
c e
r e
=
o l
S
S
T
F I
o
e t
- l l
- o
r r
t t
i e
o c
o c
w
e t
l a i
k c
i e
3
S
a n
p
o
r r
O
n i
r e i
e v
r e
m
. 2
u d
m i
m
m
e v
n i
t u
a
a
p u
t l
e t
p
m
o
6 7
d d
d n
r w
m
m
u p
l p
o d
e
i s
n i l
e d
r o
e d
n
r r
m i
c t
o
s -
n a
n a
x e
r o
e r
, 8
e t i
e d
c t
p u
w
c t
a n
e t
R
i e
t o l
r e
n o
s s
s d
s d
m
n
F
o n
t c
s t
L
i t c
n o
n o
n e
a n
0
a
S
r t
m
m
A
e i f
f l
x e
m
u a
e v
r t
i f
l l o
e t
b a
i t c
n i
o
o
P
l l o
u g
d l
c e
a
n u
e d
e d
o t
t s
B
e t
e l
e v
k s
d e
L /
i t u
a r
d e
i t c
r r
o l
t s
d e
p u
a d
A
o i t
t r a
p o
g n
n o
y b
P
a t
s t
; n
D
f o
h c
d
r t
p
p o
s i
n a
- t
e r
p i
b a
, t p
r e
e c
f s
t ,
e l
i t a
r e
v i
m i
N
, d
28
PT7A6525/6525L/6526 HDLC Controller
r e
n o
D (
R
r e
o n
transmit/receive data stream if the serial channel is operating in
a bus configuration.
This method is profitable if clock recovery should be performed
by DPLL.
Since only NRZ data encoding is supported in a bus
configuration, there are possibly long sequences without edges
in the receive data stream in case of successive “0” s received,
and the DPLL may lose synchronization.
Using the one bit insertion feature by setting the OIN bit in the
CCR1 register, however, it is guaranteed that at least after
- 5 consecutive “1”-s a “0” will appear (bit-stuffing), and
- 7 consecutive “0”-s a “1” will appear (one insertion),
and thus a correcting function of the DPLL is ensured.
Note: As the bit-stuffing method is fully transparent to the user
but not in accordance with the HDLC protocol, it can only be
applied in private systems using chip circuits exclusively.
Z
i d
M
f o
e r
a s
c
a d
A
o s
d o
L
l b
a t
A
u l
d
n i
d e
D
D
D
D
D
s i
P
o i t
n i
, g
s e
s e
s e
b a
s e
s e
c
e v
: n
n o
a r t
r c
r c
r c
r c
r c
e l
i s r
) d
p i
p i
p i
p i
p i
r t
s n
n o
l o
i t
i t
i t
i t
i t
m
n o
n o
n o
r e l
n o
n o
t i
a d
a t
i p
s n
a
e r
p o
n e
d
a r
n i
Data Sheet
o
t u
u p
s t
Ver:8