pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 2

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Introduction
The PT7A6525/6525L/6526 are designed to implement
high-speed communication links using HDLC protocols.
They profoundly reduce the hardware and software
overhead needed for serial synchronous communications.
The PT7A6525/6525L supports two completely
independent full-duplex HDLC channels (channel A and
channel B), while the PT7A6526 supports only one
(channel B). For each channel, there are an internal
Oscillator, Baud-Rate Generator (BRG), Digital Phase-
Locked Loop (DPLL), Time-Slot Assignment (TSA)
Circuitry, and a Link Controller to support various layer-
1 functions. They also directly support the X.25 LAPB,
the ISDN LAPD and SDLC (normal response mode)
protocols and are capable of handling a large set of layer-
2 protocol functions independently.
The data link controller handles all functions necessary
to establish and maintain an HDLC data link, such as
PT0017(12/05)
PT7A6525/6525L/6526 HDLC Controller
2
Associated with each serial channel are a set of
independent command and status registers and 64-byte
FIFOs each for the transmit and receive directions. Data
blocks from / to system memory can be transferred by
either Interrupt Request or Direct Memory Access
(DMA).
Associated with each serial channel are its own separate
transmit and receive DMA request lines. Thus, the
PT7A6525/6525L has a 4-channel DMA interface.
A variety of programmable telecom-specific features
allow the PT7A6525/6525L/6526 to be widely used in
time-slot oriented PCM systems, systems designed for
packet switching, and ISDN applications.
- Flag insertion and detection,
- Bit stuffing,
- CRC generation and checking, and
- Address field recognition.
Data Sheet
Ver:8