pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 35

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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• DMA Mode
If the RFIFO contains 32 bytes, the device autonomously
requests a block data transfer by DMA action of the DRQR line
at the start of the 32nd read cycle. This forces the DMA
controller to continuously perform bus cycles until 32 bytes are
transferred from the device to system memory.
If the RFIFO contains less than 32 bytes (one short frame or the
last part of a long frame), the device requests a block data
transfer according to the contents of the RFIFO as shown in
Table 9.
PT0017(12/05)
Figure 20. Frame Reception in DMA Mode
Table 9.
2
3
4
1
R
R
R
R
R
F
F
F
F
F
CPU
Interface
F I
F I
F I
F I
F I
O
O
O
O
O
C
C
C
C
C
6 1
1
8
o
o
o
o
o
4
2 ,
t n
t n
t n
t n
t n
~
~
~
n e
n e
n e
n e
n e
3 ,
5 1
DMA
Read
Cycles
(66)
7
2 3
s t
s t
s t
s t
s t
B (
B (
B (
B (
B (
y
y
y
y
y
e t
e t
e t
e t
e t
RME
RD Count
RMC
RD
RD
RD
) s
) s
) s
) s
) s
DRQR(32)
DRQR(32)
DRQR(4)
35
PT7A6525/6525L/6526 HDLC Controller
Before starting to receive the next frame, the microprocessor
must issue an RMC Command to confirm completion of the
present frame`s receive process. Otherwise, the device will not
initiate further DMA cycles by activating the DRQR line. It is
also possible to set up the DMA controller immediately after
the beginning of a frame has been detected by using the RFS
Interrupt.
Shown in Figure 20 is an example of an interrupt-controlled
reception process, supposing that a long frame (66 bytes) is
processed.
PT7A6525/6525L
PT7A6526
D
D
D
D
D
32 bytes
32 bytes
Serial
Interface
2 bytes
M
M
M
M
M
A
A
A
A
A
R
R
R
R
R
q e
q e
q e
q e
q e
2 3
6 1
e u
e u
e u
e u
e u
4
8
t s
t s
t s
t s
t s
B (
B (
B (
B (
B (
y
y
y
y
y
e t
e t
e t
e t
e t
Data Sheet
) s
) s
) s
) s
) s
Ver:8