pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 26

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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Bus Configuration
In addition to the point-to-point configuration, the PT7A6526
effectively supports point-to-multipoint (pt-mpt, or bus)
configurations by means of Internal Idle and Collision Detection/
Collision Resolution methods.
In a pt-mpt configuration comprising a central station (master)
and several peripheral stations (slaves), or in a multimaster
configuration, data transmission can be initiated by any station
over a common transmission medium (bus). In case multiple
stations attempt to transmit data simultaneously (collision), the
bus is assigned to one station by a Collision-Resolution
procedure implemented by the device. The bus assignment
function is based on a priority algorithm having both fixed and
rotating priorities that enables each station to access the bus in
a time that can be pre-determined. As a result, any number of
transmitters can be connected to the serial bus.
Requirements for bus operation are:
The bus configuration is selected via the CCR1 register.
Note: Central clock supply for each station is not necessary if
both the receive and transmit clocks are recovered by the DPLL
(clock mode 7). In this case, the DPLL also minimizes the phase
shift between the transmit clocks of the individual transmitters;
so that an opening flag sequence will be sufficient to allow
correct collision detection.
The bus mode can be operated independently of the clock mode,
e.g., in clock mode 1 (receive and transmission strobe) or clock
mode 5 (programmable time-slots).
Bus Access Procedure
The idle state of the bus is identified by eight or more successive
1s. In case of a transmit request in the device, the frame is
transmitted, and the bus is identified as busy with the first zero
of the opening flag(start flag).
After the frame has been transmitted, the bus becomes available
again by transmitting at least eight 1s.
Note: If the bus is occupied by other transmitters and/or there
is no transmit request in the device, logic 1 will be continuously
transmitted at the TxDA/TxDB output.
PT0017(12/05)
- NRZ encoding
- OR connection of data at the bus
- feedback of bus information (CxDA/CxDB input)
26
PT7A6525/6525L/6526 HDLC Controller
Collisions
During the transmission, the data transmitted from the device is
compared with the data on the bus. In case that an erroneous
bit is detected (log 1 sent and log 0 detected, or vice versa), the
frame is immediately aborted, and the idle pattern (logic 1) is
transmitted. Transmission will be initiated again by the device
as soon as possible.
A transmitted 0 is given priority over a 1 due to the OR
connection at the bus, and the individually combined stations
in the address field of the transmitted HDLC frame differ from
one another. Therefore, the fact that a collision has occurred
will be detected during transmission of the address field. The
frame of the transmitter with the highest temporary priority
(address field number) is not affected and is transmitted without
interruptions. All other transmitters terminate operation
immediately.
Note: If a wired OR connection has been realized by an external
pull-up resistor without decoupling, the data output, (TxDA/
TxDB) can be used as an open drain output and connected
directly to the CxDA, CxDB input.
Bus Timing Mode
For bus configuration, the device provides two timing modes,
differing only in the period between sending data and evaluation
of the transmitted data for collision detection.
•
•
The following two notes are for Bus Timing Mode 2.
Note 1: In Clock Mode 1 (Strobe), if receiving and transmitting
Note 2: In Clock Mode 5 (Time-slot), the delay (programmed
with the next falling clock edge. Thus one complete clock
Data is output with the falling clock edge and evaluated
period is available during data output and their evaluation.
At the point on the bus where the transmitter is connected,
the beginning of each new bit period is marked by the rising
edge of the transmit clock via the TxD pins. The level is
evaluated for CD purposes 1/2 clock period later, (half way
through the bit period) with the falling clock edge at the CxD
pins.
Timing Mode 1 (CCR1: SC1, SC0 = 01)
Timing Mode 2 (CCR1: SC1, SC0 = 11)
clock later than the delay (programmed in TTSA and
CCR2) on the transmitting end.
in RTSA and CCR2) on the receiving end should be one
strobes are used on a circuit link, the receiving strobe
should be one clock cycle after the transmitting strobe.
Data Sheet
Ver:8