pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 10

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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PT0017(12/05)
Functional Description
General
Note: Unless otherwise stated, this entire description (including
use of the word “device”) refers to the PT7A6526
communication controller, which supports a single HDLC
channel. It should be understood that the PT7A6525/6525L
contains two such “devices”.
In addition to those bit-oriented functions that are usually
included to support the HDLC protocol - such as bit stuffing,
CRC checking, flag and address recognition - the PT7A6526
provides substantial procedural support.
The device supports a special operating mode (Auto Mode)
that processes information transfer and handshaking (HDLC
protocol “I” and “S” frames) autonomously. The only
restriction is that window size (number of outstanding
unacknowledged frames) is limited to 1 (sufficient for most
applications). The detailed communication procedures are
carried out mainly between the communication controllers rather
than between the processors. Therefore (in this mode), the
microprocessor is kept informed about the the communication
procedure status only, leaving it essentially free to manage the
receive and transmit data “payload” itself. Thus, both dynamic
load on the microprocessors and software expense are greatly
reduced.
However, in order to maintain cost efficiency and flexibility,
such functions as link setup/disconnection and recovery of
protocol errors (“U” frames of HDLC protocols) are
implemented by the user’s software rather than by this
integrated hardware.
Figure 3. Frame Processing in Auto Mode
processor
Micro-
PT7A6525L
PT7A6525
PT7A6526
S Frame
I Frame
U Frame
10
PT7A6525/6525L/6526 HDLC Controller
Special operating modes are also supported; this device can
transmit or receive data packets in one of up to 64 time-slots of
programmable width (Clock Mode 5). Furthermore, it can transmit
or receive variable data portions within a defined window of
one or more clock cycles, selectable by an external strobe signal
(Clock Mode 1). Such features make it especially suitable for all
applications using Time Division Multiplex methods, such as
time-slot oriented PCM systems, systems designed for packet
switching, and ISDN applications.
An additional special feature of this device is the set of FIFO
buffers used for temporary storage of data packets transferred
between the serial communication interface and the parallel
system bus. Also, owing to this device’s overlapping input/
output operation (dual-port behavior), the maximum dynamic
load on the microprocessor is drastically reduced by transferring
the data packets block by block via Direct Memory Access
(DMA). Rather than being involved with the details of data
transfer, the microprocessor need only initiate data transmission
and monitor the status of completely received frames.
In addition to Point-to-Point configurations, this device directly
enables Point-to-Multipoint or Multimaster configurations
without additional hardware or software expense.
In Point-to-Multipoint confiurations, the PT7A6526 can be used
to enable Master as well as Slave station operation. Even when
operating as a slave station, the device can initiate the
transmission of data at any time. An internal function block
provides for Idle and Collision Detection, and Collision
Resolution, which are necessary if more than one station starts
transmitting simultaneously.
These features are integrated to support Multimaster
configurations.
PT7A6525L
PT7A6525
PT7A6526
processor
Micro-
Data Sheet
Ver:8