pt7a6525 Pericom Technology Inc, pt7a6525 Datasheet - Page 20

• Manufacturer Part Number: pt7a6525
• Description: Pt7a6525/6525l/6526 Hdlc Controller
• Manufacturer: Pericom Technology Inc

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PT0017(12/05)
DMA Interface
The PT7A6525/6525L contains a 4-channel DMA interface for
fast and effective data transfer.
For each of the two serial channels, a separate DMA Request
output for the transmit (DRQT) and receive direction (DRQR),
as well as a DMA Acknowledgement (DACK) input are
provided.
If the DMA controller is in Level-Triggered Demand Transfer
Mode, the device activates the DRQ line as long as data
transfers from/to the specific FIFO are needed.
The DMA controller executes the correct number of bus cycles.
Read cycles will be executed if DMA transfer has been requested
by the receiver, or write cycles if DMA has been requested by
the transmitter. If the DMA controller provides a DMA
acknowledgement signal (input to the device`s DACK pin), for
each bus cycle, the top of the applicable FIFO is implicitly
selected, and neither the address (via A0-A6) nor the chip select
(CS) need to be supplied (I/O to Memory transfers). If no DACK
signal is supplied, normal read/write operations (providing
addresses) must be performed (memory to memory transfers).
The device deactivates the DRQ line immediately after the last
read/write cycle of the data transfer has started.
Continuous Transmission (DMA Mode only)
If data transfer from system memory to the device is done by
DMA (DMA bit in XBCH set), the number of bytes to be
transmitted is usually defined via the Transmit Byte Count
registers (XBCH, XBCL: bits XBC11...XBC0).
However, after setting the Transmit Continuously (XC) bit
in XBCH, the byte count value will be ignored and the DMA
interface of the device will continuously request for transmit
data. At any time 32 bytes can be stored in the XFIFO.
This feature can be used to continuously transmit voice or
data onto a PCM highway (clock mode 5/extended transparent
mode). It can also be used to transmit frames exceeding the
byte count that is programmable via XBCH and XBCL (frames
with more than 4095 bytes).
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PT7A6525/6525L/6526 HDLC Controller
Note: If the XC bit is reset during continuous transmission, the
transmit byte count will become valid again, and the device will
request the number of DMA transfers programmed via
XBC11...XBC0. If this information is not provided, continuous
transmission will be terminated when a data underrun condition
occurs in the XFIFO ,i.e., the DMA controller will not permit
more data to be transferred to the device. Moreover, the device
will commence transmission of the idle pattern (continuous 1 -
s) without appending the CRC check byte.
FIFO Structure
In both the transmit and receive direction, 64-byte deep FIFOs
are provided for the intermediate storage of data between the
serial interface and the microprocessor interface. The FIFOs are
divided into two halves of 32-bytes, of which only one half is
accessible to the microprocessor or DMA controller at any one
time.
If a frame being received is at most 64 bytes long, all of it may be
stored in the RFIFO. After the first 32 bytes have been received,
the device prompts its host processor to read the 32 byte block
by means of interrupt or DMA request (RPF interrupt or
activation of DRQR line). This block remains in the RFIFO until
confirmation acknowledging transfer of the data block is
received by the device. In DMA Mode, this confirmation is
implicit after 32 bytes have been read from the RFIFO. Therefore,
in this mode, it is possible to read out the data block any number
of times until the RMC command is issued.
Figure 8 shows the configuration of the RFIFO before and after
acknowledgement.
If frames longer than 64 bytes are received, the device will
repeatedly prompt to read out 32 byte data blocks via interrupt
or DMA.
If there are several shorter frames, up to 17 of them may be
stored in the device.
If the accessible half of the RFIFO contains a frame i (or the last
part of frame i), up to 16 short frames (2 bytes for each short
frame) may be stored in the other half (i+1,...,i+n) at same time,
prior to frame i being fetched.
Data Sheet
Ver:8