m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 43

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

_____
____
ALE is an address latch enable signal used to latch the address
signal from a multiplexed signal of address and data. The latch is
transparent while ALE is “H” to let the address signal pass through
and held while ALE is “L”.
HLDA is a hold acknowledge signal and is used to notify externally
when the microcomputer receives HOLD input and enters into
hold state.
Ports P4
and lose their output pin function, but the input pin function re-
mains.
_____
HOLD is a hold request signal. It is an input signal used to put the
microcomputer in hold state. HOLD input is accepted when the in-
ternal clock
used. Ports P0, P1, P2, P3
computer stays in hold state. These ports are floating after one
cycle of the internal clock
level. At the removing of hold state, these ports are removed from
floating state after one cycle of
to “H” level.
RDY is a ready signal. If this signal goes “L”, the internal clock
stops at “L”. When
bit 7 of processor mode register to “1”,
used when slow external memory is attached.
(3) Microprocessor mode [10]
Microprocessor mode is entered by connecting the CNV
V
ming the processor mode bits to “10” after connecting the CNV
pin to V
expansion mode except that internal ROM is disabled and an ex-
ternal memory is required, and
in spite of bit 7 of processor mode register.
(4) Evaluation chip mode [11]
Evaluation chip mode is entered by applying voltage twice the V
voltage to the CNV
tion tools.
The functions of ports P0 and P3 are the same as in memory ex-
pansion mode.
Port P1 functions as an address output pin while E is “H” and as
data I/O pin of odd addresses while E is “L” regardless of the
BYTE pin level. However, if an internal memory is read, external
data is ignored while E is “L”.
Port P2 function as an address output pin while E is “H” and as
data I/O pin of even addresses while E is “L” when the BYTE pin
level is “L”. However, if an internal memory is read, external data
is ignored while E is “L”.
When the BYTE pin level is “H” or 2·V
address output pin while E is “H” and as data I/O pin of even and
odd addresses while E is “L”. However, if an internal memory is
read, external data is ignored while E is “L”.
Port P4 and its data direction register which are located at ad-
dress 0A
mode. When these addresses are accessed, the data bus width is
treated as 16 bits regardless of the BYTE pin level, and the ac-
cess cycle is treated as internal memory regardless of the wait bit.
CC
and starting from reset. It can also be entered by program-
SS
0
16
and P4
and starting from reset. This mode is similar to memory
and 0C
falls from “H” level to “L” level while the bus is not
_
1
become HOLD and RDY input pin respectively
SS
16
1
_
pin. This mode is normally used for evalua-
_
output from port P4
are treated differently in evaluation chip
_
0
_____
, and P3
later than HLDA signal changes to “L”
_____
1
later than HLDA signal changes
from port P4
_
1
_____
are floating while the micro-
_____
_
CC
____
_
1
, port P2 functions as an
output keeps on. RDY is
2
_____
is selected by setting
2
is always output
_
_
M37702M2AXXXFP, M37702M2BXXXFP
SS
____
pin to
CC
SS
____
When a voltage twice the V
the addresses corresponding to the internal ROM area are also
treated as 16-bit data bus.
The functions of ports P4
expansion mode.
Ports P4
respectively. Port P4
in spite of bit 7 of processor mode register.
The MX signal normally contains the contents of flag m, but the
contents of flag x is output if the CPU is using flag x.
QCL is the queue buffer clear signal. It becomes “H” when the in-
struction queue buffer is cleared, for example, when a jump
instruction is executed.
VDA is the valid data address signal. It becomes “H” while the
CPU is reading data from data buffer or writing data to data buffer.
It also becomes “H” when the first byte of the instruction (opera-
tion code) is read from the instruction queue buffer.
VPA is the valid program address signal. It becomes “H” while the
CPU is reading an instruction code from the instruction queue
buffer.
DBC is the debug control signal and is used for debugging. Table
5 shows the relationship between the CNV
processor modes.
Table 5. Relationship between the CNV
1
CNV
from port P4
M37702S1AFP, M37702S1BFP
2·V
V
V
CC
SS
CC
SS
2
processor modes
to P4
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
• Single-chip
• Memory expansion
• Microprocessor
• Evaluation chip
• Microprocessor
• Evaluation chip
• Evaluation chip
2
6
divided the clock to X
become
7
Mode
becomes the DBC input pin.
MITSUBISHI MICROCOMPUTERS
0
1
CC
and P4
, MX, QCL, VDA, and VPA output pins
voltage is applied to the BYTE pin,
1
____
Single-chip mode upon
starting after reset. Other
modes can be selected by
changing the processor
mode bit by software.
Microprocessor mode upon
starting after reset. Evalua-
t i o n c h i p m o d e c a n b e
selected by changing the
processor mode bit by soft-
ware.
• Evaluation chip mode only.
are the same as in memory
IN
pin by 2 is always output
SS
SS
Description
pin input levels and
pin input levels and
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