m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 25

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

(2) Event counter mode [01]
Figure 29 shows the bit configuration of the timer Bi mode register
during event counter mode. In event counter mode, the bit 0 in the
timer Bi mode register must be “1” and bit 1 must be “0”.
The input signal from the TBi
flag is “1” and counting is stopped when it is “0”. Count is per-
formed at the fall of the input signal when bits 2, and 3 are “0” and
at the rise of the input signal when bit 3 is “0” and bit 2 is “1”.
When bit 3 is “1” and bit 2 is “0”, count is performed at the rise and
fall of the input signal.
Data write, data read and timer interrupt are performed in the
same way as for timer mode.
(3) Pulse period measurement/pulse width
Figure 30 shows the bit configuration of the timer Bi mode register
during pulse period measurement/pulse width measurement
mode.
In pulse period measurement/pulse width measurement mode, bit
0 must be “0” and bit 1 must be “1”. Bits 6 and 7 are used to select
the clock source. The selected clock is counted when the count
start flag is “1” and counting stops when it is “0”.
The pulse period measurement mode is selected when bit 3 is “0”.
In pulse period measurement mode, the selected clock is counted
during the interval starting at the fall of the input signal from the
TBi
rise and the result is stored in the reload register. In this case, the
reload register acts as a buffer register.
When bit 2 is “0”, the clock is counted from the fall of the input sig-
nal to the next fall. When bit 2 is “1”, the clock is counted from the
rise of the input signal to the next rise.
In the case of counting from the fall of the input signal to the next
fall, counting is performed as follows. As shown in Figure 31,
when the fall of the input signal from TBi
tents of the counter is transferred to the reload register. Next the
counter is cleared and count is started from the next clock. When
the fall of the next input signal is detected, the contents of the
counter is transferred to the reload register once more, the
counter is cleared, and the count is started. The period from the
fall of the input signal to the next fall is measured in this way.
IN
measurement mode [10]
pin to the next fall or at the rise of the input signal to the next
IN
pin is counted when the count start
IN
pin is detected, the con-
M37702M2AXXXFP, M37702M2BXXXFP
Fig. 28 Timer Bi mode register bit configuration during timer
Fig. 29 Timer Bi mode register bit configuration during event
Fig. 30 Timer Bi mode register bit configuration during pulse
M37702S1AFP, M37702S1BFP
7 6 5 4 3 2
7 6 5 4 3 2 1 0
7
6
mode
counter mode
period measurement/pulse width measurement mode
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
5
4
3
2
1
MITSUBISHI MICROCOMPUTERS
0
0
1
1
1
0
0
0
0
Clock source selection bit
0 0 : Select f
0 1 : Select f
1 0 : Select f
1 1 : Select f
0 0 : Always “00” in timer mode
0 0 : Count at the falling edge of input
0 1 : Count at the rising edge of input
1 0 : Count at the both falling edge and
0 1 : Always “01” in event counter
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
: Not used in timer mode
: Not used in event counter mode
: Not used in timer mode and
Timer Bi overflow flag
Clock source selection bit
mode
signal
signal
rising edge of input signal
1 0 : Always “10” in pulse period
0 0 : Count from the falling edge of
0 1 : Count from the rising edge of
1 0 : Count from the falling edge of input
0 0 : Select f
0 1 : Select f
1 0 : Select f
1 1 : Select f
may be any
Timer B0 mode register 5B
Timer B1 mode register 5C
Timer B2 mode register 5D
measurement/pulse width
measurement mode
input signal to the next falling one
input signal to the next rising one
signal to the next rising one
and from the rising edge to the
next falling one
2
16
64
512
2
16
64
512
Addresses
Addresses
Addresses
5B
5C
5D
5B
5C
5D
16
16
16
16
16
16
16
16
16
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