m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 29

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

CLOCK SYNCHRONOUS SERIAL
COMMUNICATION
A case where communication is performed between two clock syn-
chronous serial I/O ports as shown in Figure 38 will be described.
(The transmission side will be denoted by subscript j and the re-
ceiving side will be denoted by subscript k.)
Bit 0 of the UARTj transmit/receive mode register and UARTk
transmit/receive mode register must be set to “1” and bits 1 and 2
must be “0”. The length of the transmission data is fixed at 8 bits.
Bit 3 of the UARTj transmit/receive mode register of the clock
sending side is cleared to “0” to select the internal clock. Bit 3 of
the UARTk transmit/receive mode register of the clock receiving
side is set to “1” to select the external clock. Bits 4, 5 and 6 are ig-
nored in-clock synchronous mode. Bit 7 must always be “0”.
The clock source is selected by bit 0 (CS
clock sending side UARTj transmit/receive control register 0. As
shown in Figure 33, the selected clock is divided by (n +1), then
by 2, passed through a transmission control circuit, and output as
transmission clock CLKj. Therefore, when the selected clock is fi,
On the clock receiving side, the CS
transmit/receive control register 0 are ignored because an external
clock is selected.
The bit 2 of the clock sending side UARTj transmit/receive control
register 0 is clear to “0” to select CTSj input. The bit 2 of the clock
receiving side is set to “1” to select RTSk output. CTS, and RTS
signals are described later.
Transmission
Transmission is started when the bit 0 (TEj flag) of UARTj trans-
mit/receive control register 1 is “1”, bit 1 (Tlj flag) of one is “0”, and
____
CTSj input is “L”. As shown in Figure 39, data is output from TxDj
pin when transmission clock CLKj changes from “H” to “L”. The
data is output from the least significant bit.
The Tlj flag indicates whether the transmission buffer register is
empty or not. It is cleared to “0” when data is written in the trans-
mission buffer register and set to “1” when the contents of the
transmission buffer register is transferred to the transmission reg-
ister.
When the transmission register becomes empty after the contents
has been transmitted, data is transferred automatically from the
transmission buffer register to the transmission register if the next
transmission start condition is satisfied. If the bit 2 of UARTj trans-
mit/receive control register 0 is “1”, CTSj input is ignored and
transmission start is controlled only by the TEj flag and TIj flag.
Once transmission has started, the TEj flag, TIj flag, and CTSj sig-
nals are ignored until data transmission completes. Therefore,
transmission is not interrupt when CTSj input is changed to “H”
during transmission.
The transmission start condition indicated by TEj flag, TIj flag, and
____
CTSj is checked while the T
Therefore, data can be transmitted continuously if the next trans-
mission data is written in the transmission buffer register and TIj
flag is cleared to “0” before the T
Bit Rate = fi
/
{(n + 1)
2}
END
j signal shown in Figure 39 is “H”.
END
____
____
0
j signal goes “H”.
_____
and CS
____
0
) and bit 1 (CS
1
bits of the UARTk
____
M37702M2AXXXFP, M37702M2BXXXFP
____
1
) of the
____
_____
The bit 3 (TxEPTYj flag) of UARTj transmit/receive control regis-
ter 0 changes to “1” at the next cycle after the T
“H” and changes to “0” when transmission starts. Therefore, this
flag can be used to determine whether data transmission has
completed.
When the TIj flag changes from “0” to “1”, the interrupt request bit
in the UARTj transmission interrupt control register is set to “1”.
Receive
Receive starts when the bit 2 (RE
control register 1 is set to “1”.
The RTS
the RE
starts. Therefore, the RTS
whether the receive register is ready to receive. It is ready when
RTS
The data from the RxD
ceive register is shifted by 1 bit each time the transmission clock
CLKj changes from “L” to “H”. When an 8-bit data is received, the
contents of the receive register is transferred to the receive buffer
register and the bit 3 (RI
register 1 is set to “1”. In other words, the setting of the RI
dicates that the receive buffer register contains the received data.
At this point, RTSj output goes “L” to indicate that the next data
can be received. When the RI
terrupt request bit in the UART
set to “1”. Bit 4 (OER
ister is set to “1” when the next data is transferred from the receive
register to the receive buffer register while RI
cates that the next data was transferred to the receive register
before the contents of the receive buffer register was read.
RI
order byte of the receive buffer register is read. The OER
also cleared when the RE
(PER
nous mode.
As shown in Figure 33, with clock synchronous serial communica-
tion, data cannot be received unless the transmitter is operating
because the receive clock is created from the transmission clock.
Therefore, the transmitter must be operating even when there is
no data to be sent from UART
k
M37702S1AFP, M37702S1BFP
and OER
_____
k
k
output is “L”.
flag), and bit 7 (SUM
k
k
flag changed to “1”. It goes back to “H” when receive
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
output is “H” when the RE
k
_____
flags are cleared automatically to “0” when the low-
k
MITSUBISHI MICROCOMPUTERS
flag) of UART
k
_____
pin is retrieved and the contents of the re-
k
k
flag) of UART
flag is cleared. Bit 5 (FER
k
k
k
k
output can be used to determine
k
flag) are ignored in clock synchro-
flag changes from “0” to “1”, the in-
to UARTj.
receive interrupt control register is
k
flag) of UART
k
k
flag is “0” and goes “L” when
transmit/receive control reg-
k
transmit/receive control
k
flag is “1”, and indi-
k
END
transmit/receive
j signal goes
k
flag), bit 6
k
k
flag in-
flag is
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