m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 33

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

If RTS
ceive control register 0 to “1”, the RTS
flag is “0”. When the RE
“L” to indicate receive ready and returns to “H” once receive has
started. In other words, RTS
ternally whether the receive register is ready to receive.
The entire transmission data bits are received when the start bit
passes the final bit of the receive block shown in Figure 35. At this
point, the contents of the receive register is transferred to the re-
ceive buffer register and the bit 3 of UART
register 1 is set. In other words, the RI
ceive buffer register contains data when it is set. If RTS
selected, RTS
to receive the next data.
The interrupt request bit in the UART
ister is set when the RI
The bit 4 (OER
set when the next data is transferred from the receive register to
the receive buffer register while the RI
when an overrun error occurs. If the OER
that the next data has been transferred to the receive buffer regis-
ter before the contents of the receive buffer register has been
read.
Bit 5 (FER
required (framing error).
Bit 6 (PER
Bit 7 (SUM
PER
mine whether there is an error.
The setting of the RIi flag, OER
is performed while transferring the contents of the receive register
to the receive buffer register. The RI
flags are cleared when the low order byte of the receive buffer reg-
ister is read or when the RE
Sleep mode
The sleep mode is used to communicate only between certain mi-
crocomputers when multiple microcomputers are connected
through serial I/O.
The sleep mode is entered when the bit 7 of UART
ceive mode register is set.
The operation of the sleep mode for an 8-bit asynchronous com-
munication is described below.
When sleep mode is selected, the contents of the receive register
is not transferred to the receive buffer register if bit 7 (bit 6 if 7-bit
asynchronous communication and bit 8 if 9-bit asychronous com-
munication) of the received data is “0”. Also the RI
PER
request bit of the UART
unchanged.
Normal receive operation takes place when bit 7 of the received
data is “1”.
The following is an example of how the sleep mode can be used.
The main microcomputer first sends data with bit 7 set to “1” and
bits 0 to 6 set to the address of the subordinate microcomputer
which wants to communicate with. Then all subordinate microcom-
____
i
i
, and the SUM
flag is set. Therefore, the SUM
i
output is selected by setting the bit 2 of UART
____
i
i
i
flag) is set when a parity error occurs.
flag) is set when the number of stop bits is less than
flag) is set when either the OER
i
output goes “L” to indicate that the register is ready
i
flag) of UART
i
flag are unchanged. Therefore, the interrupt
i
i
____
flag changes from “0” to “1”.
i
flag changes to “1”, the RTS
receive interrupt control register is also
i
i
flag is cleared.
output can be used to determine ex-
i
i
transmission control register 1 is
flag, FER
____
i
i
OER
receive interrupt control reg-
i
i
flag can be used to deter-
i
i
output is “H” when the RE
flag is “1”. In other words
flag indicates that the re-
i
i
i
, FER
transmit/receive control
i
flag, and the PER
flag is “1”, it indicates
i
flag, FER
i
____
, PER
____
i
, OER
i
i
i
output goes
transmit/re-
i
i
transmit/re-
, and SUM
flag, or the
M37702M2AXXXFP, M37702M2BXXXFP
i
output is
i
, FER
i
flag
i
,
i
i
puters receive the same data. Each subordinate microcomputer
checks the received data, clears the sleep bit if bits 0 to 6 are its
own address and sets the sleep bit if not. Next the main micro-
computer sends data with bit 7 cleared. Then the microcomputer
with the sleep bit cleared will receive the data, but the microcom-
puter with the sleep bit set will not. In this way, the main
microcomputer is able to communicate with only the designated
microcomputer.
M37702S1AFP, M37702S1BFP
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
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