m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 31

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

ASYNCHRONOUS SERIAL
COMMUNICATION
Asynchronous serial communication can be performed using 7-,
8-, or 9-bit length data. The operation is the same for all data
lengths. The following is the description for 8-bit asynchronous
communication.
With 8-bit asynchronous communication, the bit 0 of UARTi trans-
mit/receive mode register is “1“, the bit 1 is “0”, and the bit 2 is “1”.
Bit 3 is used to select an internal clock or an external clock. If bit 3
is “0”, an internal clock is selected and if bit 3 is “1”, then external
clock is selected. If an internal clock is selected, the bit 0 (CS
and bit 1 (CS
used to select the clock source. When an internal clock is selected
for asynchronous serial communication, the CLKi pin can be used
as a normal I/O pin.
Fig. 40 Transmit timing example when 8-bit asynchronous communication with parity and 1 stop bit is selected
Fig. 41 Transmit timing example when 9-bit asynchronous communication with no parity and 2 stop bits is selected
Transmission clock
Transmission clock
T
TE
CTS
T
T
TI
T
T
TE
TI
T
ENDi
X
X
i
ENDi
X
D
EPTY
X
i
i
EPTY
D
i
i
i
i
i
1
i
) of UARTi transmit/receive control register 0 are
Start bit
Start bit
Write in transmission buffer register
ST
ST
D
Write in transmission buffer register
D
0
0
D
D
1
1
D
D
2
2
D
D
3
3
(1 / f
D
D
4
4
1
D
D
, or 1 / f
5
5
(1 / f
D
D
6
6
Parity bit Stop bit
M37702M2AXXXFP, M37702M2BXXXFP
1
D
D
EXT
or 1 / f
7
7
Stop Bit Stop Bit
D
)
P SP ST
Transmission register
8
0
EXT
SP
(n + 1)
)
)
SP
Transmission register
(n + 1)
The selected internal or external clock is divided by (n +1), then by
16, and passed through a control circuit to create the UART trans-
mission clock or UART receive clock.
Therefore, the transmission speed can be changed by changing
the contents n of the bit rate generator. If the selected clock is an
internal clock fi or an external clock f
Bit 4 is the stop bit length selection bit to select 1 stop bit or 2 stop
bits.
The bit 5 is a selection bit of odd parity or even parity.
In the odd parity mode, the parity bit is adjusted so that the sum of
the 1’s in the data and parity bit is always odd.
In the even parity mode, the parity bit is adjusted so that the sum
of the 1’s in the data and parity bit is always even.
D
ST
0
16
M37702S1AFP, M37702S1BFP
Bit Rate = (f
D
D
1
0
D
D
16
Transmission
buffer register
2
1
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
D
D
2
3
D
D
i
4
3
Transmission
or f
buffer register
D
D
EXT
4
5
MITSUBISHI MICROCOMPUTERS
D
D
) / {(n + 1)
6
5
D
D
6
7
D
P SP
7
D
8
EXT
16}
SP
Stopped because TEi = “0”
,
SP
Stopped because
ST D
ST D
TEi = “0”
0
0
D
D
1
1
D
2
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