m37702s1afp Mitsumi Electronics, Corp., m37702s1afp Datasheet - Page 13

• Manufacturer Part Number: m37702s1afp
• Description: Single-chip 16-bit Cmos Microcomputer
• Manufacturer: Mitsumi Electronics, Corp.

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Table 2. Addresses of interrupt control registers
Interrupts caused by a BRK instruction and when dividing by zero
are software interrupts and are not included in this list.
Other interrupts previously mentioned are A-D converter, UART,
Timer, INT interrupts. The priority of these interrupts can be
changed by changing the priority level in the corresponding inter-
rupt control register by software.
Figure 8 shows a diagram of the interrupt priority resolution circuit.
When an interrupt is caused, the each interrupt device compares
its own priority with the priority from above and if its own priority is
higher, then it sends the priority below and requests the interrupt.
If the priorities are the same, the one above has priority.
This comparison is repeated to select the interrupt with the highest
priority among the interrupts that are being requested. Finally the
selected interrupt is compared with the processor interrupt priority
level (IPL) contained in the processor status register (PS) and the
request is accepted if it is higher than IPL and the interrupt disable
flag I is “0”. The request is not accepted if flag I is “1”. The reset,
DBC, and watchdog timer interrupts are not affected by the inter-
rupt disable flag I.
When an interrupt is accepted, the contents of the processor sta-
tus register (PS) is saved to the stack and the interrupt disable
flag I is set to “1”.
Furthermore, the interrupt request bit of the accepted interrupt is
cleared to “0” and the processor interrupt priority level (IPL) in the
processor status register (PS) is replaced by the priority level of
the accepted interrupt.
Therefore, multi-level priority interrupts are possible by resetting
the interrupt disable flag I to “0” and enable further interrupts.
For reset, DBC, watchdog timer, zero divide, and BRK instruction
interrupts, which do not have an interrupt control register, the pro-
cessor interrupt level (IPL) is set as shown in Table 3.
Priority resolution is performed by latching the interrupt request bit
and interrupt priority level so that they do not change. They are
sampled at the first half and latched at the last half of the opera-
tion code fetch cycle.
A-D conversion interrupt control register
UART0 transmit interrupt control register
UART0 receive interrupt control register
UART1 transmit interrupt control register
UART1 receive interrupt control register
Timer A0 interrupt control register
Timer A1 interrupt control register
Timer A2 interrupt control register
Timer A3 interrupt control register
Timer A4 interrupt control register
Timer B0 interrupt control register
Timer B1 interrupt control register
Timer B2 interrupt control register
INT
INT
INT
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____
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0
1
2
interrupt control register
interrupt control register
interrupt control register
Interrupt control registers
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Addresses
00007C
00007D
000070
000072
000073
000074
000075
000076
000077
000078
000079
00007A
00007B
00007E
00007F
000071
M37702M2AXXXFP, M37702M2BXXXFP
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Because priority resolution takes some time, no sampling pulse is
generated for a certain interval even if it is the next operation code
fetch cycle.
Fig. 7 Interrupt priority
Fig. 8 Interrupt priority resolution
A-D converter, UART, Timer, INT interrupts
Priority can be changed with software inside
M37702S1AFP, M37702S1BFP
Interrupt disable flag I
Watchdog
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Reset
timer
DBC
IPL
Interrupt request
MITSUBISHI MICROCOMPUTERS
Priority is determined by hardware
4
UART1 transmit
UART0 transmit
A-D conversion
UART1 receive
UART0 receive
Timer B2
Timer B1
Timer B0
Timer A4
Timer A3
Timer A2
Timer A1
Timer A0
Watchdog
timer
INT
INT
INT
3
2
1
0
4
DBC
2
Level 0
Reset
1
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