sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 9

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14941
Product data sheet
6.4 Hardware/software and time-out interrupts
6.5 Programmable baud rate generator
The interrupts are enabled by IER[0-3]. Care must be taken when handling these
interrupts. Following a reset, if Interrupt Enable Register (IER) bit 1 = 1, the SC68C2550B
will issue a Transmit Holding Register interrupt. This interrupt must be serviced prior to
continuing operations. The ISR register provides the current singular highest priority
interrupt only. A condition can exist where a higher priority interrupt may mask the lower
priority interrupt(s). Only after servicing the higher pending interrupt will the lower priority
interrupt(s) be reflected in the status register. Servicing the interrupt without investigating
further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time-Out have the same interrupt
priority (when enabled by IER[0]). The receiver issues an interrupt after the number of
characters have reached the programmed trigger level. In this case, the SC68C2550B
FIFO may hold more characters than the programmed trigger level. Following the removal
of a data byte, the user should re-check LSR[0] for additional characters. A Receive
Time-Out will not occur if the receive FIFO is empty. The time-out counter is reset at the
center of each stop bit received or each time the receive holding register (RHR) is read.
The actual time-out value is 4 character time, including data information length, start bit,
parity bit, and the size of stop bit, that is, 1 , 1.5 , or 2 bit times.
The SC68C2550B supports high speed modem technologies that have increased input
data rates by employing data compression schemes. For example, a 33.6 kbit/s modem
that employs data compression may require a 115.2 kbit/s input data rate. A 128.0 kbit/s
ISDN modem that supports data compression may need an input data rate of 460.8 kbit/s.
The SC68C2550B can support a standard data rate of 921.6 kbit/s.
A single baud rate generator is provided for the transmitter and receiver, allowing
independent TX/RX channel control. The programmable Baud Rate Generator (BRG) is
capable of operating with a frequency of up to 80 MHz. To obtain maximum data rate, it is
necessary to use full rail swing on the clock input. The SC68C2550B can be configured for
internal or external clock operation. For internal clock oscillator operation, an industry
standard microprocessor crystal is connected externally between the XTAL1 and XTAL2
pins. Alternatively, an external clock can be connected to the XTAL1 pin to clock the
internal baud rate generator for standard or custom rates (see
The generator divides the input 16 clock by any divisor from 1 to (2
SC68C2550B divides the basic external clock by 16. The basic 16 clock provides table
rates to support standard and custom applications using the same system design. The
rate table is configured via the DLL and DLM internal register functions. Customized baud
rates can be achieved by selecting the proper divisor values for the MSB and LSB
sections of baud rate generator.
Programming the baud rate generator registers DLM (MSB) and DLL (LSB) provides a
user capability for selecting the desired final baud rate. The example in
selectable baud rate table available when using a 1.8432 MHz external clock input.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 02 — 28 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C2550B
Table
16
6).
Table 6
1). The
shows the
9 of 35