sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 7

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
6. Functional description
9397 750 14941
Product data sheet
6.1 UART A-B functions
The SC68C2550B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is insured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The electronic circuitry to provide all these functions is fairly complex, especially
when manufactured on a single integrated silicon chip. The SC68C2550B represents such
an integration with greatly enhanced features. The SC68C2550B is fabricated with an
advanced CMOS process.
The SC68C2550B is an upward solution that provides a dual UART capability with
16 bytes of transmit and receive FIFO memory. The SC68C2550B is designed to work
with high speed modems and shared network environments that require fast data
processing time. Increased performance is realized in the SC68C2550B by the transmit
and receive FIFOs. This allows the external processor to handle more networking tasks
within a given time. For example, the ST16C2450 without a receive FIFO, will require
unloading of the RHR in 93 microseconds (this example uses a character length of
11 bits, including start/stop bits at 115.2 kbit/s). This means the external CPU will have to
service the receive FIFO less than every 100 microseconds. However, with the 16-byte
FIFO in the SC68C2550B, the data buffer will not require unloading/loading for 1.53 ms.
This increases the service interval, giving the external CPU additional time for other
applications and reducing the overall UART interrupt servicing time. In addition, the four
selectable receive FIFO trigger interrupt levels is uniquely provided for maximum data
throughput performance especially when operating in a multi-channel environment. The
FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The SC68C2550B is capable of operation up to 5 Mbit/s with a 80 MHz clock. With a
crystal or external clock input of 7.3728 MHz, the user can select data rates up to
460.8 kbit/s.
The rich feature set of the SC68C2550B is available through internal registers. Selectable
receive FIFO trigger levels, selectable TX and RX baud rates, and modem interface
controls are all standard features.
The UART provides the user with the capability to bi-directionally transfer information
between an external CPU, the SC68C2550B package, and an external serial device. A
logic 0 on chip select pin CS and A3 (LOW or HIGH) allows the user to configure, send
data, and/or receive data via UART channels A and B. Individual channel select functions
are shown in
Table 3:
CS
1
0
0
Channel selection using CS pin
Table
A3
-
0
1
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
3.
Rev. 02 — 28 April 2005
UART select
none
channel A
channel B
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C2550B
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