sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 17

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14941
Product data sheet
7.4 Interrupt Status Register (ISR)
Table 9:
Table 10:
The SC68C2550B provides four levels of prioritized interrupts to minimize external
software interaction. The Interrupt Status Register (ISR) provides the user with four
interrupt status bits. Performing a read cycle on the ISR will provide the user with the
highest pending interrupt level to be serviced. No other interrupts are acknowledged until
the pending interrupt is serviced. A lower level interrupt may be seen after servicing the
higher level interrupt and re-reading the interrupt status bits.
values (bit 0 to bit 3) for the four prioritized interrupt levels and the interrupt sources
associated with each of these interrupt levels.
Table 11:
Table 12:
Bit
0
FCR[7]
0
0
1
1
Priority
level
1
2
2
3
4
Bit
7:6
5:4
3:1
0
Symbol
FCR[0]
ISR[3]
0
0
1
0
0
Symbol
ISR[7:6]
ISR[5:4]
ISR[3:1]
ISR[0]
FIFO Control Register bits description
RCVR trigger levels
Interrupt source
Interrupt Status Register bits description
FCR[6]
0
1
0
1
ISR[2]
1
1
1
0
0
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Description
FIFOs enabled
logic 0 = disable the transmit and receive FIFO (normal default condition).
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to, or they will not be programmed.
Description
FIFOs enabled. These bits are set to a logic 0 when the FIFOs are not
being used in the 68C450 mode. They are set to a logic 1 when the
FIFOs are enabled in the SC68C2550B mode.
not used
INT priority bits 2 to 0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see
INT status
Rev. 02 — 28 April 2005
logic 0 or cleared = default condition
logic 0 or cleared = default condition
logic 0 = an interrupt is pending and the ISR contents may be used as
a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
ISR[1]
1
0
0
1
0
RX FIFO trigger level
01
04
08
14
ISR[0]
0
0
0
0
0
Source of the interrupt
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
RXRDY (Receive Data Time-out)
TXRDY (Transmitter Holding Register Empty)
MSR (Modem Status Register)
…continued
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Table 11
SC68C2550B
Table
shows the data
11).
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