sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 4

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
5. Pinning information
Table 2:
9397 750 14941
Product data sheet
Symbol
A0
A1
A2
A3
CS
D0 to D7
GND
IRQ
Pin description
Pin
28
27
26
11
10
44, 45, 46,
47, 48, 1,
2, 3
17, 24
30
5.1 Pinning
5.2 Pin description
Type
I
I
I
I
I
I/O
I
O
Fig 2. Pin configuration for LQFP48
Description
Address 0 select bit. Internal register address selection.
Address 1 select bit. Internal register address selection.
Address 2 select bit. Internal register address selection.
Address 3. A3 is used to select Channel A or Channel B. A logic LOW selects
Channel A, and a logic HIGH selects Channel B. (See
Chip Select (active LOW). This pin enables data transfers between the user CPU and
the SC68C2550B for the channel(s) addressed. Individual UART sections (A, B) are
addressed by A3. See
Data bus (bi-directional). These pins are the 8-bit, 3-state data bus for transferring
information to or from the controlling CPU. D0 is the least significant bit and the first data
bit in a transmit or receive serial data stream.
Signal and power ground.
Interrupt Request. Interrupts from UART channels A-B are wire-ORed internally to
function as a single IRQ interrupt. This pin transitions to a logic 0 (if enabled by the
interrupt enable register) whenever a UART channel(s) requires service. Individual
channel interrupt status can be determined by addressing each channel through its
associated internal register, using CS and A3. An external pull-up resistor must be
connected between this pin and V
TXRDYB
OP2B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
RXB
RXA
TXA
TXB
n.c.
CS
D5
D6
D7
A3
Rev. 02 — 28 April 2005
10
11
12
1
2
3
4
5
6
7
8
9
Table
3.
SC68C2550BIB48
CC
.
Table
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C2550B
002aab335
3.)
36
35
34
33
32
31
30
29
28
27
26
25
RESET
DTRB
DTRA
RTSA
OP2A
RXRDYA
IRQ
n.c.
A0
A1
A2
n.c.
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