sc68c2550b NXP Semiconductors, sc68c2550b Datasheet - Page 11

• Manufacturer Part Number: sc68c2550b
• Description: Sc68c2550b 5 V, 3.3 V And 2.5 V Dual Uart, 5 Mbit/s Max. , With 16-byte Fifos And Motorola Up Interface
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 14941
Product data sheet
6.7 Loop-back mode
The internal loop-back capability allows on-board diagnostics. In the Loop-back mode, the
normal modem interface pins are disconnected and reconfigured for loop-back internally
(see
In the Loop-back mode, the transmitter output (TX) and the receiver input (RX) are
disconnected from their associated interface pins, and instead are connected together
internally. The CTS, DSR, CD, and RI are disconnected from their normal modem control
inputs pins, and instead are connected internally to RTS, DTR, MCR[3] (OP2) and
MCR[2] (OP1). Loop-back test data is entered into the transmit holding register via the
user data bus interface, D0 to D7. The transmit UART serializes the data and passes the
serial data to the receive UART via the internal loop-back connection. The receive UART
converts the serial data back into parallel data that is then made available at the user data
interface D0 to D7. The user optionally compares the received data to the initial
transmitted data for verifying error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
Figure
4). MCR[3:0] register bits are used for controlling loop-back diagnostic testing.
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Rev. 02 — 28 April 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SC68C2550B
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